mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-20 16:20:11 +01:00
radeon: drop CS2 into CS, remove start/end offset
This commit is contained in:
parent
12e68f8059
commit
4b10ddff78
6 changed files with 4 additions and 125 deletions
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@ -37,8 +37,6 @@
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struct radeon_cs_reloc {
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struct radeon_cs_reloc {
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struct radeon_bo *bo;
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struct radeon_bo *bo;
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uint32_t start_offset;
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uint32_t end_offset;
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uint32_t read_domain;
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uint32_t read_domain;
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uint32_t write_domain;
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uint32_t write_domain;
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uint32_t flags;
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uint32_t flags;
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@ -69,8 +67,6 @@ struct radeon_cs_funcs {
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int (*cs_write_dword)(struct radeon_cs *cs, uint32_t dword);
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int (*cs_write_dword)(struct radeon_cs *cs, uint32_t dword);
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int (*cs_write_reloc)(struct radeon_cs *cs,
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int (*cs_write_reloc)(struct radeon_cs *cs,
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struct radeon_bo *bo,
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struct radeon_bo *bo,
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uint32_t start_offset,
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uint32_t end_offset,
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uint32_t read_domain,
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uint32_t read_domain,
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uint32_t write_domain,
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uint32_t write_domain,
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uint32_t flags);
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uint32_t flags);
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@ -108,16 +104,12 @@ static inline int radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
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static inline int radeon_cs_write_reloc(struct radeon_cs *cs,
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static inline int radeon_cs_write_reloc(struct radeon_cs *cs,
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struct radeon_bo *bo,
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struct radeon_bo *bo,
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uint32_t start_offset,
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uint32_t end_offset,
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uint32_t read_domain,
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uint32_t read_domain,
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uint32_t write_domain,
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uint32_t write_domain,
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uint32_t flags)
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uint32_t flags)
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{
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{
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return cs->csm->funcs->cs_write_reloc(cs,
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return cs->csm->funcs->cs_write_reloc(cs,
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bo,
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bo,
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start_offset,
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end_offset,
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read_domain,
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read_domain,
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write_domain,
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write_domain,
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flags);
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flags);
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@ -43,8 +43,6 @@
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#pragma pack(1)
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#pragma pack(1)
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struct cs_reloc_gem {
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struct cs_reloc_gem {
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uint32_t handle;
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uint32_t handle;
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uint32_t start_offset;
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uint32_t end_offset;
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uint32_t read_domain;
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uint32_t read_domain;
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uint32_t write_domain;
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uint32_t write_domain;
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uint32_t flags;
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uint32_t flags;
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@ -127,8 +125,6 @@ static int cs_gem_write_dword(struct radeon_cs *cs, uint32_t dword)
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static int cs_gem_write_reloc(struct radeon_cs *cs,
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static int cs_gem_write_reloc(struct radeon_cs *cs,
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struct radeon_bo *bo,
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struct radeon_bo *bo,
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uint32_t start_offset,
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uint32_t end_offset,
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uint32_t read_domain,
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uint32_t read_domain,
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uint32_t write_domain,
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uint32_t write_domain,
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uint32_t flags)
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uint32_t flags)
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@ -151,13 +147,6 @@ static int cs_gem_write_reloc(struct radeon_cs *cs,
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if (write_domain == RADEON_GEM_DOMAIN_CPU) {
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if (write_domain == RADEON_GEM_DOMAIN_CPU) {
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return -EINVAL;
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return -EINVAL;
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}
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}
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/* check reloc window */
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if (end_offset > bo->size) {
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return -EINVAL;
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}
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if (start_offset > end_offset) {
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return -EINVAL;
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}
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/* check if bo is already referenced */
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/* check if bo is already referenced */
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for(i = 0; i < cs->crelocs; i++) {
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for(i = 0; i < cs->crelocs; i++) {
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idx = i * 6;
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idx = i * 6;
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@ -177,13 +166,6 @@ static int cs_gem_write_reloc(struct radeon_cs *cs,
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}
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}
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reloc->read_domain |= read_domain;
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reloc->read_domain |= read_domain;
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reloc->write_domain |= write_domain;
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reloc->write_domain |= write_domain;
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/* update start and end offset */
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if (start_offset < reloc->start_offset) {
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reloc->start_offset = start_offset;
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}
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if (end_offset > reloc->end_offset) {
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reloc->end_offset = end_offset;
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}
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/* update flags */
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/* update flags */
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reloc->flags |= (flags & reloc->flags);
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reloc->flags |= (flags & reloc->flags);
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/* write relocation packet */
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/* write relocation packet */
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@ -215,8 +197,6 @@ static int cs_gem_write_reloc(struct radeon_cs *cs,
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idx = (csg->base.crelocs++) * 6;
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idx = (csg->base.crelocs++) * 6;
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reloc = (struct cs_reloc_gem*)&csg->relocs[idx];
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reloc = (struct cs_reloc_gem*)&csg->relocs[idx];
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reloc->handle = bo->handle;
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reloc->handle = bo->handle;
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reloc->start_offset = start_offset;
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reloc->end_offset = end_offset;
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reloc->read_domain = read_domain;
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reloc->read_domain = read_domain;
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reloc->write_domain = write_domain;
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reloc->write_domain = write_domain;
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reloc->flags = flags;
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reloc->flags = flags;
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@ -29,11 +29,11 @@
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#include "radeon_drv.h"
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#include "radeon_drv.h"
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#include "r300_reg.h"
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#include "r300_reg.h"
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int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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{
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{
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struct drm_radeon_cs_parser parser;
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struct drm_radeon_cs_parser parser;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_radeon_cs2 *cs = data;
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struct drm_radeon_cs *cs = data;
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uint32_t cs_id;
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uint32_t cs_id;
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struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
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struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
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uint64_t *chunk_array;
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uint64_t *chunk_array;
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@ -98,11 +98,6 @@ int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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if (parser.chunks[i].chunk_id == RADEON_CHUNK_ID_IB)
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if (parser.chunks[i].chunk_id == RADEON_CHUNK_ID_IB)
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parser.ib_index = i;
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parser.ib_index = i;
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if (parser.chunks[i].chunk_id == RADEON_CHUNK_ID_OLD) {
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parser.ib_index = i;
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parser.reloc_index = -1;
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}
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parser.chunks[i].length_dw = user_chunk.length_dw;
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parser.chunks[i].length_dw = user_chunk.length_dw;
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parser.chunks[i].chunk_data = (uint32_t *)(unsigned long)user_chunk.chunk_data;
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parser.chunks[i].chunk_data = (uint32_t *)(unsigned long)user_chunk.chunk_data;
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@ -111,7 +106,6 @@ int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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switch(parser.chunks[i].chunk_id) {
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switch(parser.chunks[i].chunk_id) {
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case RADEON_CHUNK_ID_IB:
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case RADEON_CHUNK_ID_IB:
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case RADEON_CHUNK_ID_OLD:
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if (size == 0) {
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if (size == 0) {
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r = -EINVAL;
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r = -EINVAL;
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goto out;
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goto out;
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@ -178,80 +172,6 @@ out:
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return r;
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return r;
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}
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}
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int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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{
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struct drm_radeon_cs_parser parser;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_radeon_cs *cs = data;
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uint32_t *packets = NULL;
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uint32_t cs_id;
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long size;
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int r;
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struct drm_radeon_kernel_chunk chunk_fake[1];
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/* set command stream id to 0 which is fake id */
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cs_id = 0;
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cs->cs_id = cs_id;
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if (dev_priv == NULL) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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if (!cs->dwords) {
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return 0;
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}
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/* limit cs to 64K ib */
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if (cs->dwords > (16 * 1024)) {
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return -EINVAL;
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}
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/* copy cs from userspace maybe we should copy into ib to save
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* one copy but ib will be mapped wc so not good for cmd checking
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* somethings worth testing i guess (Jerome)
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*/
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size = cs->dwords * sizeof(uint32_t);
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packets = drm_alloc(size, DRM_MEM_DRIVER);
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if (packets == NULL) {
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return -ENOMEM;
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}
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if (DRM_COPY_FROM_USER(packets, (void __user *)(unsigned long)cs->packets, size)) {
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r = -EFAULT;
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goto out;
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}
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chunk_fake[0].chunk_id = RADEON_CHUNK_ID_OLD;
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chunk_fake[0].length_dw = cs->dwords;
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chunk_fake[0].kdata = packets;
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parser.dev = dev;
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parser.file_priv = fpriv;
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parser.num_chunks = 1;
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parser.chunks = chunk_fake;
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parser.ib_index = 0;
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parser.reloc_index = -1;
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/* get ib */
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r = dev_priv->cs.ib_get(&parser);
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if (r) {
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goto out;
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}
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/* now parse command stream */
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r = dev_priv->cs.parse(&parser);
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if (r) {
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goto out;
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}
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/* emit cs id sequence */
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dev_priv->cs.id_emit(&parser, &cs_id);
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COMMIT_RING();
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cs->cs_id = cs_id;
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out:
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dev_priv->cs.ib_free(&parser);
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drm_free(packets, size, DRM_MEM_DRIVER);
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return r;
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}
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/* for non-mm */
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/* for non-mm */
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static int radeon_nomm_relocate(struct drm_radeon_cs_parser *parser, uint32_t *reloc, uint32_t *offset)
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static int radeon_nomm_relocate(struct drm_radeon_cs_parser *parser, uint32_t *reloc, uint32_t *offset)
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{
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{
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@ -513,8 +513,7 @@ typedef struct {
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#define DRM_RADEON_GEM_SET_DOMAIN 0x23
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#define DRM_RADEON_GEM_SET_DOMAIN 0x23
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#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
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#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
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#define DRM_RADEON_CS 0x25
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#define DRM_RADEON_CS 0x26
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#define DRM_RADEON_CS2 0x26
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#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
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#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
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#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
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#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
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@ -554,8 +553,6 @@ typedef struct {
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#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
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#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
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#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering)
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#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering)
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#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
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#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
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#define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2)
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typedef struct drm_radeon_init {
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typedef struct drm_radeon_init {
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enum {
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enum {
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@ -870,16 +867,8 @@ struct drm_radeon_gem_pwrite {
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/* New interface which obsolete all previous interface.
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/* New interface which obsolete all previous interface.
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*/
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*/
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struct drm_radeon_cs {
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uint32_t dwords;
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uint32_t cs_id;
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uint64_t packets;
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};
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#define RADEON_CHUNK_ID_RELOCS 0x01
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#define RADEON_CHUNK_ID_RELOCS 0x01
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#define RADEON_CHUNK_ID_IB 0x02
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#define RADEON_CHUNK_ID_IB 0x02
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#define RADEON_CHUNK_ID_OLD 0xff
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struct drm_radeon_cs_chunk {
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struct drm_radeon_cs_chunk {
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uint32_t chunk_id;
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uint32_t chunk_id;
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@ -887,7 +876,7 @@ struct drm_radeon_cs_chunk {
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uint64_t chunk_data;
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uint64_t chunk_data;
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};
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};
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struct drm_radeon_cs2 {
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struct drm_radeon_cs {
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uint32_t num_chunks;
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uint32_t num_chunks;
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uint32_t cs_id;
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uint32_t cs_id;
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uint64_t chunks; /* this points to uint64_t * which point to
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uint64_t chunks; /* this points to uint64_t * which point to
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@ -1739,7 +1739,6 @@ extern int radeon_master_create(struct drm_device *dev, struct drm_master *maste
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extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
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extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
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extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
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extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
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extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
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extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
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extern int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
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extern int radeon_cs_init(struct drm_device *dev);
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extern int radeon_cs_init(struct drm_device *dev);
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void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
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void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
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void radeon_init_memory_map(struct drm_device *dev);
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void radeon_init_memory_map(struct drm_device *dev);
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@ -3291,7 +3291,6 @@ struct drm_ioctl_desc radeon_ioctls[] = {
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DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_RENDERING, radeon_gem_wait_rendering, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_RENDERING, radeon_gem_wait_rendering, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_CS2, radeon_cs2_ioctl, DRM_AUTH),
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};
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};
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int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
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int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
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