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https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-09 08:38:23 +02:00
Added Fcol to state
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parent
ecea34eb94
commit
49f497a1cb
2 changed files with 28 additions and 18 deletions
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@ -118,7 +118,8 @@ typedef struct _xf86drmClipRectRec {
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#define MGA_CTXREG_WFLAG 6
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#define MGA_CTXREG_TDUAL0 7
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#define MGA_CTXREG_TDUAL1 8
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#define MGA_CTX_SETUP_SIZE 9
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#define MGA_CTXREG_FCOL 9
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#define MGA_CTX_SETUP_SIZE 10
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/* 2d state
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*/
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@ -47,12 +47,12 @@ static void mgaEmitClipRect( drm_mga_private_t *dev_priv, xf86drmClipRectRec *bo
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PRIMGETPTR( dev_priv );
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/* Force reset of dwgctl (eliminates clip disable) */
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag - 1 );
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PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag - 1 );
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PRIMOUTREG( MGAREG_DMAPAD, dev_priv->last_sync_tag - 1 );
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PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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PRIMOUTREG( MGAREG_CXBNDRY, ((box->x2)<<16)|(box->x1) );
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PRIMOUTREG( MGAREG_YTOP, box->y1 * dev_priv->stride/2 );
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PRIMOUTREG( MGAREG_YBOT, box->y2 * dev_priv->stride/2 );
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@ -83,8 +83,13 @@ static void mgaEmitContext(drm_mga_private_t *dev_priv )
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PRIMOUTREG( MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG] );
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PRIMOUTREG( MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0] );
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PRIMOUTREG( MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1] );
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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}
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PRIMOUTREG( MGAREG_FCOL, regs[MGA_CTXREG_FCOL] );
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} else {
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PRIMOUTREG( MGAREG_FCOL, regs[MGA_CTXREG_FCOL] );
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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}
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PRIMADVANCE( dev_priv );
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}
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@ -437,7 +442,7 @@ static inline void mga_dma_dispatch_tex_blit( drm_device_t *dev,
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unsigned int destOrg )
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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int use_agp = PDEA_pagpxfer_enable;
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int use_agp = PDEA_pagpxfer_enable | 0x00000001;
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u16 y2;
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PRIMLOCALS;
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@ -451,7 +456,8 @@ static inline void mga_dma_dispatch_tex_blit( drm_device_t *dev,
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PRIMOUTREG( MGAREG_DSTORG, destOrg);
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PRIMOUTREG( MGAREG_MACCESS, 0x00000002);
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PRIMOUTREG( MGAREG_SRCORG, bus_address | use_agp);
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DRM_DEBUG("srcorg : %lx\n", bus_address | use_agp);
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PRIMOUTREG( MGAREG_SRCORG, (u32) bus_address | use_agp);
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PRIMOUTREG( MGAREG_AR5, 64);
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PRIMOUTREG( MGAREG_PITCH, 64);
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@ -586,12 +592,12 @@ static inline void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
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else
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cmd = MGA_CLEAR_CMD | DC_atype_rstr;
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primary_needed = nbox * 60;
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if(primary_needed == 0) primary_needed = 60;
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primary_needed = nbox * 70;
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if(primary_needed == 0) primary_needed = 70;
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PRIM_OVERFLOW(dev, dev_priv, primary_needed);
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PRIMGETPTR( dev_priv );
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dev_priv->last_sync_tag = mga_create_sync_tag(dev);
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for (i = 0 ; i < nbox ; i++) {
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unsigned int height = pbox[i].y2 - pbox[i].y1;
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@ -642,9 +648,9 @@ static inline void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
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/* Force reset of DWGCTL */
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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@ -693,13 +699,13 @@ static inline void mga_dma_dispatch_swap( drm_device_t *dev )
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PRIMOUTREG(MGAREG_FXBNDRY, pbox[i].x1|((pbox[i].x2 - 1)<<16));
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PRIMOUTREG(MGAREG_YDSTLEN+MGAREG_MGA_EXEC, (pbox[i].y1<<16)|h);
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}
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/* Force reset of DWGCTL */
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
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PRIMOUTREG( MGAREG_SRCORG, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_DMAPAD, 0);
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@ -777,23 +783,26 @@ int mga_iload(struct inode *inode, struct file *filp,
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drm_mga_iload_t iload;
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unsigned long bus_address;
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DRM_DEBUG("Starting Iload\n");
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copy_from_user_ret(&iload, (drm_mga_iload_t *)arg, sizeof(iload),
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-EFAULT);
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buf = dma->buflist[ iload.idx ];
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buf_priv = buf->dev_private;
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bus_address = buf->bus_address;
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DRM_DEBUG("bus_address %lx, length %d, destorg : %x\n",
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bus_address, iload.length, iload.destOrg);
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if(mgaVerifyIload(dev_priv,
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iload.destOrg,
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bus_address,
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bus_address,
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iload.destOrg,
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iload.length)) {
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mga_freelist_put(dev, buf);
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return -EINVAL;
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}
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sarea_priv->dirty |= MGA_UPLOAD_CTX;
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mga_dma_dispatch_tex_blit(dev, bus_address, iload.length,
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iload.destOrg);
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buf_priv->my_freelist->age = dev_priv->last_sync_tag;
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