mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-06 03:38:03 +02:00
Remove multiple states code
This commit is contained in:
Keith Whitwell
parent
cf438cfe77
commit
3f1341a7fb
9 changed files with 133 additions and 463 deletions
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@ -542,6 +542,7 @@ static void i810EmitContextVerified( drm_device_t *dev,
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OUT_RING( code[i] );
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j++;
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}
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else printk("constext state dropped!!!\n");
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}
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if (j & 1)
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@ -572,6 +573,7 @@ static void i810EmitTexVerified( drm_device_t *dev,
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OUT_RING( code[i] );
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j++;
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}
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else printk("texture state dropped!!!\n");
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}
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if (j & 1)
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@ -597,6 +599,8 @@ static void i810EmitDestVerified( drm_device_t *dev,
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OUT_RING( CMD_OP_DESTBUFFER_INFO );
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OUT_RING( tmp );
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}
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else
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printk("buffer state dropped\n");
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/* invarient:
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*/
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@ -618,24 +622,30 @@ static void i810EmitDestVerified( drm_device_t *dev,
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static void i810EmitState( drm_device_t *dev,
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drm_i810_state_t *state,
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unsigned int dirty )
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static void i810EmitState( drm_device_t *dev )
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{
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drm_i810_private_t *dev_priv = dev->dev_private;
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drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
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unsigned int dirty = sarea_priv->dirty;
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if (dirty & I810_UPLOAD_BUFFERS) {
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i810EmitDestVerified( dev, state->BufferSetup );
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i810EmitDestVerified( dev, sarea_priv->BufferState );
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sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
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}
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if (dirty & I810_UPLOAD_CTX) {
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i810EmitContextVerified( dev, state->Setup );
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i810EmitContextVerified( dev, sarea_priv->ContextState );
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sarea_priv->dirty &= ~I810_UPLOAD_CTX;
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}
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if (dirty & I810_UPLOAD_TEX0) {
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i810EmitTexVerified( dev, state->TexSetup[0] );
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i810EmitTexVerified( dev, sarea_priv->TexState[0] );
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sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
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}
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if (dirty & I810_UPLOAD_TEX1) {
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i810EmitTexVerified( dev, state->TexSetup[1] );
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i810EmitTexVerified( dev, sarea_priv->TexState[1] );
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sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
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}
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}
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@ -757,10 +767,7 @@ static void i810_dma_dispatch_swap( drm_device_t *dev )
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static void i810_dma_dispatch_vertex(drm_device_t *dev,
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drm_buf_t *buf,
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int discard,
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drm_i810_prim_t *prim,
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unsigned int nrprim,
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drm_i810_state_t *state,
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unsigned int nrstate )
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int used)
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{
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drm_i810_private_t *dev_priv = dev->dev_private;
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drm_i810_buf_priv_t *buf_priv = buf->dev_private;
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@ -768,70 +775,58 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev,
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drm_clip_rect_t *box = sarea_priv->boxes;
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int nbox = sarea_priv->nbox;
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unsigned long address = (unsigned long)buf->bus_address;
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unsigned long bufstart = address - dev->agp->base;
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char *buf_virtual = (char *)buf_priv->virtual;
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unsigned int i;
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unsigned long start = address - dev->agp->base;
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int i = 0;
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RING_LOCALS;
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if (nbox > I810_NR_SAREA_CLIPRECTS)
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nrprim = 0;
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i810_kernel_lost_context(dev);
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for (i = 0 ; i < nrprim ; i++, prim++) {
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int j = 0;
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if (nbox > I810_NR_SAREA_CLIPRECTS)
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nbox = I810_NR_SAREA_CLIPRECTS;
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/* printk("prim %d start %x fin %x\n", i, prim->start, */
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/* prim->finish); */
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if (used > 4*1024)
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used = 0;
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if ((unsigned)prim->start >= I810_DMA_BUF_SZ ||
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prim->start >= prim->finish ||
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(prim->start & 0x7) != 0x4) {
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/* printk("alignment/other\n"); */
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continue;
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if (sarea_priv->dirty)
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i810EmitState( dev );
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DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
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address, used, nbox);
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if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
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*(u32 *)buf_priv->virtual = (GFX_OP_PRIMITIVE |
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sarea_priv->vertex_prim |
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((used/4)-2));
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if (used & 4) {
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*(u32 *)((u32)buf_priv->virtual + used) = 0;
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used += 4;
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}
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if (prim->dirty && prim->stateidx < nrstate) {
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i810EmitState( dev,
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&state[(int)prim->stateidx],
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prim->dirty );
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}
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*(int *)&buf_virtual[prim->start-4] =
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(GFX_OP_PRIMITIVE | (((int)prim->prim) << 18) |
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((prim->finish - prim->start)/4-1));
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if (prim->finish & 0x4) {
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*(int *)&buf_virtual[prim->finish] = 0;
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prim->finish += 4;
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}
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i810_unmap_buffer(buf);
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}
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if (used) {
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do {
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if (j < nbox) {
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if (i < nbox) {
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BEGIN_LP_RING(4);
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OUT_RING( GFX_OP_SCISSOR |
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SC_UPDATE_SCISSOR |
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OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
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SC_ENABLE );
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OUT_RING( GFX_OP_SCISSOR_INFO );
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OUT_RING( box[j].x1 | (box[j].y1<<16) );
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OUT_RING( (box[j].x2-1) | ((box[j].y2-1)<<16) );
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OUT_RING( box[i].x1 | (box[i].y1<<16) );
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OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) );
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ADVANCE_LP_RING();
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if (nbox == 1) nbox = 0;
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}
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BEGIN_LP_RING(4);
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OUT_RING( CMD_OP_BATCH_BUFFER );
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OUT_RING( (bufstart + prim->start - 4) |
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BB1_PROTECTED );
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OUT_RING( (bufstart + prim->finish - 4) );
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OUT_RING( start | BB1_PROTECTED );
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OUT_RING( start + used - 4 );
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OUT_RING( 0 );
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ADVANCE_LP_RING();
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} while (++j < nbox);
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}
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} while (++i < nbox);
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}
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if (discard) {
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dev_priv->counter++;
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@ -839,7 +834,7 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev,
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(void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
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I810_BUF_HARDWARE);
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BEGIN_LP_RING( 8 );
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BEGIN_LP_RING(8);
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OUT_RING( CMD_STORE_DWORD_IDX );
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OUT_RING( 20 );
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OUT_RING( dev_priv->counter );
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@ -858,6 +853,8 @@ void i810_dma_quiescent(drm_device_t *dev)
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drm_i810_private_t *dev_priv = dev->dev_private;
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RING_LOCALS;
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/* printk("%s\n", __FUNCTION__); */
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i810_kernel_lost_context(dev);
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BEGIN_LP_RING(4);
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@ -877,6 +874,8 @@ static int i810_flush_queue(drm_device_t *dev)
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int i, ret = 0;
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RING_LOCALS;
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/* printk("%s\n", __FUNCTION__); */
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i810_kernel_lost_context(dev);
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BEGIN_LP_RING(2);
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@ -946,32 +945,8 @@ int i810_flush_ioctl(struct inode *inode, struct file *filp,
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}
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/* Copy sarea data into temporary structs.
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*/
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void i810_copy_state( drm_i810_sarea_t *sarea, drm_i810_state_t *state )
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{
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if (sarea->dirty & I810_UPLOAD_CTX)
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memcpy(state->Setup, sarea->ContextState,
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sizeof(state->Setup));
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if (sarea->dirty & I810_UPLOAD_BUFFERS)
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memcpy(state->BufferSetup, sarea->BufferState,
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sizeof(state->BufferSetup));
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if (sarea->dirty & I810_UPLOAD_TEX0)
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memcpy(state->TexSetup[0], sarea->TexState[0],
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sizeof(state->TexSetup[0]));
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if (sarea->dirty & I810_UPLOAD_TEX1)
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memcpy(state->TexSetup[1], sarea->TexState[1],
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sizeof(state->TexSetup[1]));
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}
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/* Obsolete, backwards compatibility ioctl:
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*/
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int i810_dma_vertex(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg)
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unsigned int cmd, unsigned long arg)
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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@ -981,12 +956,6 @@ int i810_dma_vertex(struct inode *inode, struct file *filp,
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drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
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dev_priv->sarea_priv;
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drm_i810_vertex_t vertex;
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drm_buf_t *buf;
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drm_i810_buf_priv_t *buf_priv;
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drm_i810_state_t tmpstate;
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drm_i810_prim_t tmpprim;
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/* printk("%s\n", __FUNCTION__); */
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if (copy_from_user(&vertex, (drm_i810_vertex_t *)arg, sizeof(vertex)))
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return -EFAULT;
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@ -996,117 +965,25 @@ int i810_dma_vertex(struct inode *inode, struct file *filp,
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return -EINVAL;
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}
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buf = dma->buflist[ vertex.idx ];
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buf_priv = buf->dev_private;
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DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
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vertex.idx, vertex.used, vertex.discard);
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if (vertex.idx < 0 || vertex.idx >= I810_DMA_BUF_NR) {
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DRM_ERROR("i810_dma_vertex bad buffer idx\n");
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return -EINVAL;
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}
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if (sarea_priv->dirty)
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i810_copy_state( sarea_priv, &tmpstate );
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if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
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tmpprim.start = 0;
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tmpprim.finish = vertex.used;
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tmpprim.prim = (char) sarea_priv->vertex_prim;
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tmpprim.dirty = (char) sarea_priv->dirty;
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tmpprim.stateidx = 0;
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i810_dma_dispatch_vertex( dev, buf,
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vertex.discard,
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&tmpprim, 1,
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&tmpstate, 1 );
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if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
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i810_unmap_buffer(buf);
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}
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i810_dma_dispatch_vertex( dev,
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dma->buflist[ vertex.idx ],
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vertex.discard, vertex.used );
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atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
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atomic_inc(&dev->counts[_DRM_STAT_DMA]);
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sarea_priv->last_enqueue = dev_priv->counter-1;
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sarea_priv->last_dispatch = (int) hw_status[5];
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return 0;
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}
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int i810_dma_vertex2(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg)
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_device_dma_t *dma = dev->dma;
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drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
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u32 *hw_status = (u32 *)dev_priv->hw_status_page;
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drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
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dev_priv->sarea_priv;
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drm_i810_vertex2_t vertex;
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drm_buf_t *buf;
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drm_i810_buf_priv_t *buf_priv;
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/* printk("%s\n", __FUNCTION__); */
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if (copy_from_user(&vertex, (drm_i810_vertex2_t *)arg, sizeof(vertex)))
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return -EFAULT;
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if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
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DRM_ERROR("i810_dma_vertex2 called without lock held\n");
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return -EINVAL;
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}
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if (vertex.idx >= I810_DMA_BUF_NR) {
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DRM_ERROR("i810_dma_vertex2 bad buffer idx\n");
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return -EINVAL;
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}
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/* printk("%s buf %d nstates %d nprim %d\n", */
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/* __FUNCTION__, */
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/* vertex.idx, */
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/* vertex.nr_states, */
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/* vertex.nr_prims ); */
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buf = dma->buflist[ vertex.idx ];
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buf_priv = buf->dev_private;
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if (vertex.nr_states) {
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if (vertex.nr_states >= I810_MAX_STATES)
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return -EINVAL;
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if (copy_from_user(dev_priv->statetmp,
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vertex.state_address,
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vertex.nr_states * sizeof(drm_i810_state_t)))
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return -EFAULT;
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}
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if (vertex.nr_prims) {
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if (vertex.nr_prims >= I810_MAX_PRIMS)
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return -EINVAL;
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if (copy_from_user(dev_priv->primtmp,
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vertex.prim_address,
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vertex.nr_prims * sizeof(drm_i810_prim_t)))
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return -EFAULT;
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}
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i810_dma_dispatch_vertex( dev, buf,
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vertex.discard,
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dev_priv->primtmp,
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vertex.nr_prims,
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dev_priv->statetmp,
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vertex.nr_states );
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if (buf_priv->currently_mapped == I810_BUF_MAPPED)
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i810_unmap_buffer(buf);
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atomic_inc(&dev->counts[_DRM_STAT_DMA]);
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sarea_priv->last_enqueue = dev_priv->counter-1;
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sarea_priv->last_dispatch = (int) hw_status[5];
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return 0;
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}
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int i810_clear_bufs(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg)
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{
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@ -191,13 +191,6 @@ typedef struct _drm_i810_copy_t {
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void *address; /* Address to copy from */
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} drm_i810_copy_t;
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typedef struct _drm_i810_state {
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unsigned int Setup[I810_CTX_SETUP_SIZE];
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unsigned int BufferSetup[I810_DEST_SETUP_SIZE];
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unsigned int TexSetup[2][I810_TEX_SETUP_SIZE];
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} drm_i810_state_t;
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#define PR_TRIANGLES (0x0)
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#define PR_TRISTRIP_0 (0x1)
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#define PR_TRISTRIP_1 (0x2)
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@ -207,35 +200,6 @@ typedef struct _drm_i810_state {
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#define PR_LINESTRIP (0x6)
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#define PR_RECTS (0x7)
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typedef struct _drm_i810_prim {
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int start;
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int finish;
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char prim;
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char dirty;
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char stateidx;
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} drm_i810_prim_t;
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#define I810_MAX_PRIMS 100
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#define I810_MAX_STATES 20
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/* Still uses the sarea to pass cliprects (fix?). State and primitive
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* information are passed directly as pointers to userspace data.
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* Copying of vertex data is performed by this ioctl as well.
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*
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* This obsoletes _drm_i810_vertex, _drm_i810_copy and the state and
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* primitive fields in the sarea.
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*/
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typedef struct _drm_i810_vertex2 {
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unsigned int idx; /* buffer index */
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unsigned int discard; /* client is finished with the buffer? */
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void *vertex_address;
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unsigned int nr_states;
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drm_i810_state_t *state_address;
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unsigned int nr_prims;
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drm_i810_prim_t *prim_address;
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} drm_i810_vertex2_t;
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typedef struct drm_i810_dma {
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void *virtual;
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@ -44,8 +44,8 @@
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/* Interface history
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*
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* 1.1 - XFree 4.1
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* 1.2 - Add i810_dma_vertex2 ioctl,
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* - Disable copying code (leave stub ioctls for backwards compatibility)
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* 1.2 - Disable copying code (leave stub ioctls for backwards compatibility)
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* - Remove requirement for interrupt (leave stubs again)
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*
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*/
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#define DRIVER_MAJOR 1
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@ -61,8 +61,7 @@
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[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)] = { i810_copybuf, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX2)] = { i810_dma_vertex2, 1, 0 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 },
|
||||
|
||||
|
||||
#define __HAVE_COUNTERS 4
|
||||
|
|
|
|||
|
|
@ -74,11 +74,6 @@ typedef struct drm_i810_private {
|
|||
int w, h;
|
||||
int pitch;
|
||||
|
||||
/* Temporaries to hold userspace data before submitting to the
|
||||
* ring.
|
||||
*/
|
||||
drm_i810_state_t statetmp[I810_MAX_STATES];
|
||||
drm_i810_prim_t primtmp[I810_MAX_STATES];
|
||||
} drm_i810_private_t;
|
||||
|
||||
/* i810_dma.c */
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@
|
|||
* be cleaner.
|
||||
*/
|
||||
#define __HAVE_DMA_IRQ 1
|
||||
#define __HAVE_DMA_IRQ_BH 1 /* ??? */
|
||||
#define __HAVE_DMA_IRQ_BH 0 /* ??? */
|
||||
#define __HAVE_SHARED_IRQ 1
|
||||
#define DRIVER_PREINSTALL() return 0
|
||||
#define DRIVER_POSTINSTALL() return 0
|
||||
|
|
|
|||
249
linux/i810_dma.c
249
linux/i810_dma.c
|
|
@ -542,6 +542,7 @@ static void i810EmitContextVerified( drm_device_t *dev,
|
|||
OUT_RING( code[i] );
|
||||
j++;
|
||||
}
|
||||
else printk("constext state dropped!!!\n");
|
||||
}
|
||||
|
||||
if (j & 1)
|
||||
|
|
@ -572,6 +573,7 @@ static void i810EmitTexVerified( drm_device_t *dev,
|
|||
OUT_RING( code[i] );
|
||||
j++;
|
||||
}
|
||||
else printk("texture state dropped!!!\n");
|
||||
}
|
||||
|
||||
if (j & 1)
|
||||
|
|
@ -597,6 +599,8 @@ static void i810EmitDestVerified( drm_device_t *dev,
|
|||
OUT_RING( CMD_OP_DESTBUFFER_INFO );
|
||||
OUT_RING( tmp );
|
||||
}
|
||||
else
|
||||
printk("buffer state dropped\n");
|
||||
|
||||
/* invarient:
|
||||
*/
|
||||
|
|
@ -618,24 +622,30 @@ static void i810EmitDestVerified( drm_device_t *dev,
|
|||
|
||||
|
||||
|
||||
static void i810EmitState( drm_device_t *dev,
|
||||
drm_i810_state_t *state,
|
||||
unsigned int dirty )
|
||||
static void i810EmitState( drm_device_t *dev )
|
||||
{
|
||||
drm_i810_private_t *dev_priv = dev->dev_private;
|
||||
drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
unsigned int dirty = sarea_priv->dirty;
|
||||
|
||||
if (dirty & I810_UPLOAD_BUFFERS) {
|
||||
i810EmitDestVerified( dev, state->BufferSetup );
|
||||
i810EmitDestVerified( dev, sarea_priv->BufferState );
|
||||
sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
|
||||
}
|
||||
|
||||
if (dirty & I810_UPLOAD_CTX) {
|
||||
i810EmitContextVerified( dev, state->Setup );
|
||||
i810EmitContextVerified( dev, sarea_priv->ContextState );
|
||||
sarea_priv->dirty &= ~I810_UPLOAD_CTX;
|
||||
}
|
||||
|
||||
if (dirty & I810_UPLOAD_TEX0) {
|
||||
i810EmitTexVerified( dev, state->TexSetup[0] );
|
||||
i810EmitTexVerified( dev, sarea_priv->TexState[0] );
|
||||
sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
|
||||
}
|
||||
|
||||
if (dirty & I810_UPLOAD_TEX1) {
|
||||
i810EmitTexVerified( dev, state->TexSetup[1] );
|
||||
i810EmitTexVerified( dev, sarea_priv->TexState[1] );
|
||||
sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -757,10 +767,7 @@ static void i810_dma_dispatch_swap( drm_device_t *dev )
|
|||
static void i810_dma_dispatch_vertex(drm_device_t *dev,
|
||||
drm_buf_t *buf,
|
||||
int discard,
|
||||
drm_i810_prim_t *prim,
|
||||
unsigned int nrprim,
|
||||
drm_i810_state_t *state,
|
||||
unsigned int nrstate )
|
||||
int used)
|
||||
{
|
||||
drm_i810_private_t *dev_priv = dev->dev_private;
|
||||
drm_i810_buf_priv_t *buf_priv = buf->dev_private;
|
||||
|
|
@ -768,70 +775,58 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev,
|
|||
drm_clip_rect_t *box = sarea_priv->boxes;
|
||||
int nbox = sarea_priv->nbox;
|
||||
unsigned long address = (unsigned long)buf->bus_address;
|
||||
unsigned long bufstart = address - dev->agp->base;
|
||||
char *buf_virtual = (char *)buf_priv->virtual;
|
||||
unsigned int i;
|
||||
unsigned long start = address - dev->agp->base;
|
||||
int i = 0;
|
||||
RING_LOCALS;
|
||||
|
||||
if (nbox > I810_NR_SAREA_CLIPRECTS)
|
||||
nrprim = 0;
|
||||
|
||||
i810_kernel_lost_context(dev);
|
||||
|
||||
for (i = 0 ; i < nrprim ; i++, prim++) {
|
||||
int j = 0;
|
||||
if (nbox > I810_NR_SAREA_CLIPRECTS)
|
||||
nbox = I810_NR_SAREA_CLIPRECTS;
|
||||
|
||||
/* printk("prim %d start %x fin %x\n", i, prim->start, */
|
||||
/* prim->finish); */
|
||||
if (used > 4*1024)
|
||||
used = 0;
|
||||
|
||||
if ((unsigned)prim->start >= I810_DMA_BUF_SZ ||
|
||||
prim->start >= prim->finish ||
|
||||
(prim->start & 0x7) != 0x4) {
|
||||
/* printk("alignment/other\n"); */
|
||||
continue;
|
||||
if (sarea_priv->dirty)
|
||||
i810EmitState( dev );
|
||||
|
||||
DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
|
||||
address, used, nbox);
|
||||
|
||||
if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
|
||||
*(u32 *)buf_priv->virtual = (GFX_OP_PRIMITIVE |
|
||||
sarea_priv->vertex_prim |
|
||||
((used/4)-2));
|
||||
|
||||
if (used & 4) {
|
||||
*(u32 *)((u32)buf_priv->virtual + used) = 0;
|
||||
used += 4;
|
||||
}
|
||||
|
||||
if (prim->dirty && prim->stateidx < nrstate) {
|
||||
i810EmitState( dev,
|
||||
&state[(int)prim->stateidx],
|
||||
prim->dirty );
|
||||
}
|
||||
|
||||
*(int *)&buf_virtual[prim->start-4] =
|
||||
(GFX_OP_PRIMITIVE | (((int)prim->prim) << 18) |
|
||||
((prim->finish - prim->start)/4-1));
|
||||
|
||||
|
||||
if (prim->finish & 0x4) {
|
||||
*(int *)&buf_virtual[prim->finish] = 0;
|
||||
prim->finish += 4;
|
||||
}
|
||||
|
||||
|
||||
i810_unmap_buffer(buf);
|
||||
}
|
||||
|
||||
if (used) {
|
||||
do {
|
||||
if (j < nbox) {
|
||||
if (i < nbox) {
|
||||
BEGIN_LP_RING(4);
|
||||
OUT_RING( GFX_OP_SCISSOR |
|
||||
SC_UPDATE_SCISSOR |
|
||||
OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
|
||||
SC_ENABLE );
|
||||
OUT_RING( GFX_OP_SCISSOR_INFO );
|
||||
OUT_RING( box[j].x1 | (box[j].y1<<16) );
|
||||
OUT_RING( (box[j].x2-1) | ((box[j].y2-1)<<16) );
|
||||
OUT_RING( box[i].x1 | (box[i].y1<<16) );
|
||||
OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) );
|
||||
ADVANCE_LP_RING();
|
||||
if (nbox == 1) nbox = 0;
|
||||
}
|
||||
|
||||
BEGIN_LP_RING(4);
|
||||
OUT_RING( CMD_OP_BATCH_BUFFER );
|
||||
OUT_RING( (bufstart + prim->start - 4) |
|
||||
BB1_PROTECTED );
|
||||
OUT_RING( (bufstart + prim->finish - 4) );
|
||||
OUT_RING( start | BB1_PROTECTED );
|
||||
OUT_RING( start + used - 4 );
|
||||
OUT_RING( 0 );
|
||||
ADVANCE_LP_RING();
|
||||
} while (++j < nbox);
|
||||
}
|
||||
|
||||
} while (++i < nbox);
|
||||
}
|
||||
|
||||
if (discard) {
|
||||
dev_priv->counter++;
|
||||
|
|
@ -839,7 +834,7 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev,
|
|||
(void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
|
||||
I810_BUF_HARDWARE);
|
||||
|
||||
BEGIN_LP_RING( 8 );
|
||||
BEGIN_LP_RING(8);
|
||||
OUT_RING( CMD_STORE_DWORD_IDX );
|
||||
OUT_RING( 20 );
|
||||
OUT_RING( dev_priv->counter );
|
||||
|
|
@ -858,6 +853,8 @@ void i810_dma_quiescent(drm_device_t *dev)
|
|||
drm_i810_private_t *dev_priv = dev->dev_private;
|
||||
RING_LOCALS;
|
||||
|
||||
/* printk("%s\n", __FUNCTION__); */
|
||||
|
||||
i810_kernel_lost_context(dev);
|
||||
|
||||
BEGIN_LP_RING(4);
|
||||
|
|
@ -877,6 +874,8 @@ static int i810_flush_queue(drm_device_t *dev)
|
|||
int i, ret = 0;
|
||||
RING_LOCALS;
|
||||
|
||||
/* printk("%s\n", __FUNCTION__); */
|
||||
|
||||
i810_kernel_lost_context(dev);
|
||||
|
||||
BEGIN_LP_RING(2);
|
||||
|
|
@ -946,32 +945,8 @@ int i810_flush_ioctl(struct inode *inode, struct file *filp,
|
|||
}
|
||||
|
||||
|
||||
/* Copy sarea data into temporary structs.
|
||||
*/
|
||||
void i810_copy_state( drm_i810_sarea_t *sarea, drm_i810_state_t *state )
|
||||
{
|
||||
if (sarea->dirty & I810_UPLOAD_CTX)
|
||||
memcpy(state->Setup, sarea->ContextState,
|
||||
sizeof(state->Setup));
|
||||
|
||||
if (sarea->dirty & I810_UPLOAD_BUFFERS)
|
||||
memcpy(state->BufferSetup, sarea->BufferState,
|
||||
sizeof(state->BufferSetup));
|
||||
|
||||
if (sarea->dirty & I810_UPLOAD_TEX0)
|
||||
memcpy(state->TexSetup[0], sarea->TexState[0],
|
||||
sizeof(state->TexSetup[0]));
|
||||
|
||||
if (sarea->dirty & I810_UPLOAD_TEX1)
|
||||
memcpy(state->TexSetup[1], sarea->TexState[1],
|
||||
sizeof(state->TexSetup[1]));
|
||||
}
|
||||
|
||||
|
||||
/* Obsolete, backwards compatibility ioctl:
|
||||
*/
|
||||
int i810_dma_vertex(struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg)
|
||||
unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
|
|
@ -981,12 +956,6 @@ int i810_dma_vertex(struct inode *inode, struct file *filp,
|
|||
drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
|
||||
dev_priv->sarea_priv;
|
||||
drm_i810_vertex_t vertex;
|
||||
drm_buf_t *buf;
|
||||
drm_i810_buf_priv_t *buf_priv;
|
||||
drm_i810_state_t tmpstate;
|
||||
drm_i810_prim_t tmpprim;
|
||||
|
||||
/* printk("%s\n", __FUNCTION__); */
|
||||
|
||||
if (copy_from_user(&vertex, (drm_i810_vertex_t *)arg, sizeof(vertex)))
|
||||
return -EFAULT;
|
||||
|
|
@ -996,117 +965,25 @@ int i810_dma_vertex(struct inode *inode, struct file *filp,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
buf = dma->buflist[ vertex.idx ];
|
||||
buf_priv = buf->dev_private;
|
||||
DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
|
||||
vertex.idx, vertex.used, vertex.discard);
|
||||
|
||||
if (vertex.idx < 0 || vertex.idx >= I810_DMA_BUF_NR) {
|
||||
DRM_ERROR("i810_dma_vertex bad buffer idx\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (sarea_priv->dirty)
|
||||
i810_copy_state( sarea_priv, &tmpstate );
|
||||
if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
|
||||
|
||||
tmpprim.start = 0;
|
||||
tmpprim.finish = vertex.used;
|
||||
tmpprim.prim = (char) sarea_priv->vertex_prim;
|
||||
tmpprim.dirty = (char) sarea_priv->dirty;
|
||||
tmpprim.stateidx = 0;
|
||||
|
||||
i810_dma_dispatch_vertex( dev, buf,
|
||||
vertex.discard,
|
||||
&tmpprim, 1,
|
||||
&tmpstate, 1 );
|
||||
|
||||
if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
|
||||
i810_unmap_buffer(buf);
|
||||
}
|
||||
i810_dma_dispatch_vertex( dev,
|
||||
dma->buflist[ vertex.idx ],
|
||||
vertex.discard, vertex.used );
|
||||
|
||||
atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
|
||||
atomic_inc(&dev->counts[_DRM_STAT_DMA]);
|
||||
|
||||
sarea_priv->last_enqueue = dev_priv->counter-1;
|
||||
sarea_priv->last_dispatch = (int) hw_status[5];
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int i810_dma_vertex2(struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
|
||||
u32 *hw_status = (u32 *)dev_priv->hw_status_page;
|
||||
drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
|
||||
dev_priv->sarea_priv;
|
||||
drm_i810_vertex2_t vertex;
|
||||
drm_buf_t *buf;
|
||||
drm_i810_buf_priv_t *buf_priv;
|
||||
|
||||
/* printk("%s\n", __FUNCTION__); */
|
||||
|
||||
if (copy_from_user(&vertex, (drm_i810_vertex2_t *)arg, sizeof(vertex)))
|
||||
return -EFAULT;
|
||||
|
||||
if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
||||
DRM_ERROR("i810_dma_vertex2 called without lock held\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (vertex.idx >= I810_DMA_BUF_NR) {
|
||||
DRM_ERROR("i810_dma_vertex2 bad buffer idx\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
/* printk("%s buf %d nstates %d nprim %d\n", */
|
||||
/* __FUNCTION__, */
|
||||
/* vertex.idx, */
|
||||
/* vertex.nr_states, */
|
||||
/* vertex.nr_prims ); */
|
||||
|
||||
buf = dma->buflist[ vertex.idx ];
|
||||
buf_priv = buf->dev_private;
|
||||
|
||||
if (vertex.nr_states) {
|
||||
if (vertex.nr_states >= I810_MAX_STATES)
|
||||
return -EINVAL;
|
||||
|
||||
if (copy_from_user(dev_priv->statetmp,
|
||||
vertex.state_address,
|
||||
vertex.nr_states * sizeof(drm_i810_state_t)))
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (vertex.nr_prims) {
|
||||
if (vertex.nr_prims >= I810_MAX_PRIMS)
|
||||
return -EINVAL;
|
||||
|
||||
if (copy_from_user(dev_priv->primtmp,
|
||||
vertex.prim_address,
|
||||
vertex.nr_prims * sizeof(drm_i810_prim_t)))
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
i810_dma_dispatch_vertex( dev, buf,
|
||||
vertex.discard,
|
||||
dev_priv->primtmp,
|
||||
vertex.nr_prims,
|
||||
dev_priv->statetmp,
|
||||
vertex.nr_states );
|
||||
|
||||
if (buf_priv->currently_mapped == I810_BUF_MAPPED)
|
||||
i810_unmap_buffer(buf);
|
||||
|
||||
atomic_inc(&dev->counts[_DRM_STAT_DMA]);
|
||||
|
||||
sarea_priv->last_enqueue = dev_priv->counter-1;
|
||||
sarea_priv->last_dispatch = (int) hw_status[5];
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int i810_clear_bufs(struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -191,13 +191,6 @@ typedef struct _drm_i810_copy_t {
|
|||
void *address; /* Address to copy from */
|
||||
} drm_i810_copy_t;
|
||||
|
||||
|
||||
typedef struct _drm_i810_state {
|
||||
unsigned int Setup[I810_CTX_SETUP_SIZE];
|
||||
unsigned int BufferSetup[I810_DEST_SETUP_SIZE];
|
||||
unsigned int TexSetup[2][I810_TEX_SETUP_SIZE];
|
||||
} drm_i810_state_t;
|
||||
|
||||
#define PR_TRIANGLES (0x0)
|
||||
#define PR_TRISTRIP_0 (0x1)
|
||||
#define PR_TRISTRIP_1 (0x2)
|
||||
|
|
@ -207,35 +200,6 @@ typedef struct _drm_i810_state {
|
|||
#define PR_LINESTRIP (0x6)
|
||||
#define PR_RECTS (0x7)
|
||||
|
||||
typedef struct _drm_i810_prim {
|
||||
int start;
|
||||
int finish;
|
||||
char prim;
|
||||
char dirty;
|
||||
char stateidx;
|
||||
} drm_i810_prim_t;
|
||||
|
||||
|
||||
#define I810_MAX_PRIMS 100
|
||||
#define I810_MAX_STATES 20
|
||||
|
||||
/* Still uses the sarea to pass cliprects (fix?). State and primitive
|
||||
* information are passed directly as pointers to userspace data.
|
||||
* Copying of vertex data is performed by this ioctl as well.
|
||||
*
|
||||
* This obsoletes _drm_i810_vertex, _drm_i810_copy and the state and
|
||||
* primitive fields in the sarea.
|
||||
*/
|
||||
typedef struct _drm_i810_vertex2 {
|
||||
unsigned int idx; /* buffer index */
|
||||
unsigned int discard; /* client is finished with the buffer? */
|
||||
void *vertex_address;
|
||||
unsigned int nr_states;
|
||||
drm_i810_state_t *state_address;
|
||||
unsigned int nr_prims;
|
||||
drm_i810_prim_t *prim_address;
|
||||
} drm_i810_vertex2_t;
|
||||
|
||||
|
||||
typedef struct drm_i810_dma {
|
||||
void *virtual;
|
||||
|
|
|
|||
|
|
@ -44,8 +44,8 @@
|
|||
/* Interface history
|
||||
*
|
||||
* 1.1 - XFree 4.1
|
||||
* 1.2 - Add i810_dma_vertex2 ioctl,
|
||||
* - Disable copying code (leave stub ioctls for backwards compatibility)
|
||||
* 1.2 - Disable copying code (leave stub ioctls for backwards compatibility)
|
||||
* - Remove requirement for interrupt (leave stubs again)
|
||||
*
|
||||
*/
|
||||
#define DRIVER_MAJOR 1
|
||||
|
|
@ -61,8 +61,7 @@
|
|||
[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)] = { i810_copybuf, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX2)] = { i810_dma_vertex2, 1, 0 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 },
|
||||
|
||||
|
||||
#define __HAVE_COUNTERS 4
|
||||
|
|
|
|||
|
|
@ -74,11 +74,6 @@ typedef struct drm_i810_private {
|
|||
int w, h;
|
||||
int pitch;
|
||||
|
||||
/* Temporaries to hold userspace data before submitting to the
|
||||
* ring.
|
||||
*/
|
||||
drm_i810_state_t statetmp[I810_MAX_STATES];
|
||||
drm_i810_prim_t primtmp[I810_MAX_STATES];
|
||||
} drm_i810_private_t;
|
||||
|
||||
/* i810_dma.c */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue