mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-01-03 15:10:18 +01:00
debug commit for jeff
This commit is contained in:
Keith Whitwell
parent
9cdbd34ae3
commit
3e69b2967e
7 changed files with 116 additions and 229 deletions
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@ -32,19 +32,19 @@
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#define __NO_VERSION__
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#include "drmP.h"
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#include "mga_drv.h"
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#include "i810_drv.h"
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#include <linux/interrupt.h> /* For task queue support */
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#define MGA_REG(reg) 0 /* for now */
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#define MGA_BASE(reg) ((unsigned long) \
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dev->maplist[MGA_REG(reg)]->handle)
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#define MGA_ADDR(reg) (MGA_BASE(reg) + MGA_OFF(reg))
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#define MGA_DEREF(reg) *(__volatile__ int *)MGA_ADDR(reg)
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#define MGA_READ(reg) MGA_DEREF(reg)
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#define MGA_WRITE(reg,val) do { MGA_DEREF(reg) = val; } while (0)
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#define I810_REG(reg) 0 /* for now */
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#define I810_BASE(reg) ((unsigned long) \
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dev->maplist[I810_REG(reg)]->handle)
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#define I810_ADDR(reg) (I810_BASE(reg) + I810_OFF(reg))
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#define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg)
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#define I810_READ(reg) I810_DEREF(reg)
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#define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0)
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typedef _mga_primary_buffer {
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typedef _i810_primary_buffer {
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u32 *head;
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u32 *dma_ptr;
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u8 tempIndex[4];
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@ -52,9 +52,9 @@ typedef _mga_primary_buffer {
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int num_dwords;
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int max_dwords;
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unsigned long phys_head;
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} mgaPrimBuf;
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} i810PrimBuf;
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static mgaPrimBuf buffer;
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static i810PrimBuf buffer;
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typedef enum {
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TT_GENERAL,
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TT_BLIT,
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@ -83,7 +83,7 @@ buffer.num_dwords += 5; \
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#define CHECK_OVERFLOW(length) do { \
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if((buffer.max_dwords - buffer.num_dwords) < length) { \
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mga_prim_overflow(); \
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i810_prim_overflow(); \
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} \
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}while(0)
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@ -96,14 +96,14 @@ static inline void i810_dma_dispatch(drm_device_t *dev, unsigned long address,
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int use_agp = PDEA_pagpxfer_enable;
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CHECK_OVERFLOW(10);
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DMAOUTREG(MGAREG_DMAPAD, 0);
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DMAOUTREG(MGAREG_DMAPAD, 0);
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DMAOUTREG(MGAREG_SECADDRESS, address | transferType);
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DMAOUTREG(MGAREG_SECEND, (address + length) | use_agp);
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DMAOUTREG(MGAREG_DMAPAD, 0);
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DMAOUTREG(MGAREG_DMAPAD, 0);
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DMAOUTREG(MGAREG_DWGSYNC, 0);
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DMAOUTREG(MGAREG_SOFTRAP, 0);
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DMAOUTREG(I810REG_DMAPAD, 0);
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DMAOUTREG(I810REG_DMAPAD, 0);
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DMAOUTREG(I810REG_SECADDRESS, address | transferType);
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DMAOUTREG(I810REG_SECEND, (address + length) | use_agp);
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DMAOUTREG(I810REG_DMAPAD, 0);
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DMAOUTREG(I810REG_DMAPAD, 0);
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DMAOUTREG(I810REG_DWGSYNC, 0);
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DMAOUTREG(I810REG_SOFTRAP, 0);
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/* Needs to write out to PRIMEND */
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}
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@ -159,7 +159,7 @@ static void i810_dma_service(int irq, void *device, struct pt_regs *regs)
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GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */
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GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8);
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GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001);
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if (mga_dma_is_ready(dev)) {
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if (i810_dma_is_ready(dev)) {
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/* Free previous buffer */
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if (test_and_set_bit(0, &dev->dma_flag)) {
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atomic_inc(&dma->total_missed_free);
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@ -227,7 +227,7 @@ static int i810_do_dma(drm_device_t *dev, int locked)
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return 0;
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}
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if (!mga_dma_is_ready(dev)) {
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if (!i810_dma_is_ready(dev)) {
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clear_bit(0, &dev->dma_flag);
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return -EBUSY;
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}
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@ -273,7 +273,7 @@ static int i810_do_dma(drm_device_t *dev, int locked)
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buf->time_dispatched = get_cycles();
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#endif
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mga_dma_dispatch(dev, address, length);
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i810_dma_dispatch(dev, address, length);
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drm_free_buffer(dev, dma->this_buffer);
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dma->this_buffer = buf;
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@ -346,14 +346,14 @@ again:
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or the DMA engine wasn't ready. Try
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again. */
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atomic_inc(&dma->total_tried);
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if (!(retcode = mga_do_dma(dev, locked))) {
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if (!(retcode = i810_do_dma(dev, locked))) {
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atomic_inc(&dma->total_hit);
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++processed;
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}
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} else {
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do {
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next = drm_select_queue(dev,
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mga_dma_schedule_timer_wrapper);
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i810_dma_schedule_timer_wrapper);
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if (next >= 0) {
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q = dev->queuelist[next];
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buf = drm_waitlist_get(&q->waitlist);
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@ -366,7 +366,7 @@ again:
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}
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} while (next >= 0 && !dma->next_buffer);
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if (dma->next_buffer) {
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if (!(retcode = mga_do_dma(dev, locked))) {
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if (!(retcode = i810_do_dma(dev, locked))) {
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++processed;
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}
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}
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@ -375,9 +375,9 @@ again:
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if (--expire) {
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if (missed != atomic_read(&dma->total_missed_sched)) {
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atomic_inc(&dma->total_lost);
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if (mga_dma_is_ready(dev)) goto again;
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if (i810_dma_is_ready(dev)) goto again;
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}
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if (processed && mga_dma_is_ready(dev)) {
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if (processed && i810_dma_is_ready(dev)) {
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atomic_inc(&dma->total_lost);
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processed = 0;
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goto again;
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@ -506,7 +506,7 @@ static int i810_dma_priority(drm_device_t *dev, drm_dma_t *d)
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buf->time_queued = get_cycles();
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buf->time_dispatched = buf->time_queued;
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#endif
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mga_dma_dispatch(dev, address, length);
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i810_dma_dispatch(dev, address, length);
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atomic_add(length, &dma->total_bytes);
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atomic_inc(&dma->total_dmas);
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@ -519,7 +519,7 @@ static int i810_dma_priority(drm_device_t *dev, drm_dma_t *d)
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cleanup:
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if (last_buf) {
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mga_dma_ready(dev);
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i810_dma_ready(dev);
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drm_free_buffer(dev, last_buf);
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}
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@ -551,7 +551,7 @@ static int i810_dma_send_buffers(drm_device_t *dev, drm_dma_t *d)
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return retcode;
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}
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mga_dma_schedule(dev, 0);
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i810_dma_schedule(dev, 0);
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if (d->flags & _DRM_DMA_BLOCK) {
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DRM_DEBUG("%d waiting\n", current->pid);
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@ -621,9 +621,9 @@ int i810_dma(struct inode *inode, struct file *filp, unsigned int cmd,
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if (d.send_count) {
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if (d.flags & _DRM_DMA_PRIORITY)
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retcode = mga_dma_priority(dev, &d);
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retcode = i810_dma_priority(dev, &d);
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else
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retcode = mga_dma_send_buffers(dev, &d);
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retcode = i810_dma_send_buffers(dev, &d);
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}
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d.granted_count = 0;
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@ -665,16 +665,16 @@ int i810_irq_install(drm_device_t *dev, int irq)
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dev->tq.next = NULL;
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dev->tq.sync = 0;
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dev->tq.routine = mga_dma_schedule_tq_wrapper;
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dev->tq.routine = i810_dma_schedule_tq_wrapper;
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dev->tq.data = dev;
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/* Before installing handler */
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MGA_WRITE(MGAREG_IEN, 0);
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I810_WRITE(I810REG_IEN, 0);
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/* Install handler */
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if ((retcode = request_irq(dev->irq,
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mga_dma_service,
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i810_dma_service,
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0,
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dev->devname,
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dev))) {
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@ -685,7 +685,7 @@ int i810_irq_install(drm_device_t *dev, int irq)
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}
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/* After installing handler */
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MGA_WRITE(MGAREG_IEN, 0x00000001);
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I810_WRITE(I810REG_IEN, 0x00000001);
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return 0;
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}
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@ -702,7 +702,7 @@ int i810_irq_uninstall(drm_device_t *dev)
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DRM_DEBUG("%d\n", irq);
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MGA_WRITE(MGAREG_IEN, 0);
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I810_WRITE(I810REG_IEN, 0);
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free_irq(irq, dev);
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return 0;
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@ -721,11 +721,11 @@ int i810_control(struct inode *inode, struct file *filp, unsigned int cmd,
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switch (ctl.func) {
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case DRM_INST_HANDLER:
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if ((retcode = mga_irq_install(dev, ctl.irq)))
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if ((retcode = i810_irq_install(dev, ctl.irq)))
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return retcode;
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break;
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case DRM_UNINST_HANDLER:
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if ((retcode = mga_irq_uninstall(dev)))
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if ((retcode = i810_irq_uninstall(dev)))
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return retcode;
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break;
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default:
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@ -812,9 +812,9 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
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if (!ret) {
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if (lock.flags & _DRM_LOCK_READY)
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mga_dma_ready(dev);
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i810_dma_ready(dev);
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if (lock.flags & _DRM_LOCK_QUIESCENT)
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mga_dma_quiescent(dev);
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i810_dma_quiescent(dev);
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}
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DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
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@ -37,7 +37,7 @@ EXPORT_SYMBOL(i810_init);
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EXPORT_SYMBOL(i810_cleanup);
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#define I810_NAME "i810"
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#define I810_DESC "Matrox g200/g400"
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#define I810_DESC "Intel i810"
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#define I810_DATE "19991213"
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#define I810_MAJOR 0
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#define I810_MINOR 0
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@ -71,14 +71,19 @@ static drm_ioctl_desc_t i810_ioctls[] = {
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[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 },
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#if 0
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[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { i810_control, 1, 1 },
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#endif
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[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 },
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#if 0
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[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { i810_addbufs, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { i810_markbufs, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { i810_infobufs, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { i810_mapbufs, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { i810_freebufs, 1, 0 },
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#endif
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[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { i810_addctx, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { i810_rmctx, 1, 1 },
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@ -99,7 +104,7 @@ static drm_ioctl_desc_t i810_ioctls[] = {
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire, 1, 1},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release, 1, 1},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable, 1, 1},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 1},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 0},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1},
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_unbind, 1, 1},
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@ -228,7 +233,7 @@ static int i810_takedown(drm_device_t *dev)
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DRM_DEBUG("\n");
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if (dev->irq) i810_irq_uninstall(dev);
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/* if (dev->irq) i810_irq_uninstall(dev); */
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down(&dev->struct_sem);
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del_timer(&dev->timer);
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@ -552,33 +557,7 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
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lock.context, current->pid, dev->lock.hw_lock->lock,
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lock.flags);
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#if 0
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/* dev->queue_count == 0 right now for
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i810. FIXME? */
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if (lock.context < 0 || lock.context >= dev->queue_count)
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return -EINVAL;
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#endif
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if (!ret) {
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#if 0
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if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)
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!= lock.context) {
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long j = jiffies - dev->lock.lock_time;
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if (lock.context == i810_res_ctx.handle &&
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j >= 0 && j < DRM_LOCK_SLICE) {
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/* Can't take lock if we just had it and
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there is contention. */
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DRM_DEBUG("%d (pid %d) delayed j=%d dev=%d jiffies=%d\n",
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lock.context, current->pid, j,
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dev->lock.lock_time, jiffies);
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current->state = TASK_INTERRUPTIBLE;
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current->policy |= SCHED_YIELD;
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schedule_timeout(DRM_LOCK_SLICE-j);
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DRM_DEBUG("jiffies=%d\n", jiffies);
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}
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}
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#endif
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add_wait_queue(&dev->lock.lock_queue, &entry);
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for (;;) {
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if (!dev->lock.hw_lock) {
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@ -597,9 +576,7 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
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/* Contention */
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atomic_inc(&dev->total_sleeps);
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current->state = TASK_INTERRUPTIBLE;
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#if 1
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current->policy |= SCHED_YIELD;
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#endif
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schedule();
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if (signal_pending(current)) {
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ret = -ERESTARTSYS;
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@ -610,58 +587,20 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
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remove_wait_queue(&dev->lock.lock_queue, &entry);
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}
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#if 0
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if (!ret && dev->last_context != lock.context &&
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lock.context != i810_res_ctx.handle &&
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dev->last_context != i810_res_ctx.handle) {
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add_wait_queue(&dev->context_wait, &entry);
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current->state = TASK_INTERRUPTIBLE;
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/* PRE: dev->last_context != lock.context */
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i810_context_switch(dev, dev->last_context, lock.context);
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/* POST: we will wait for the context
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switch and will dispatch on a later call
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when dev->last_context == lock.context
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NOTE WE HOLD THE LOCK THROUGHOUT THIS
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TIME! */
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current->policy |= SCHED_YIELD;
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schedule();
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current->state = TASK_RUNNING;
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remove_wait_queue(&dev->context_wait, &entry);
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if (signal_pending(current)) {
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ret = -EINTR;
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} else if (dev->last_context != lock.context) {
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DRM_ERROR("Context mismatch: %d %d\n",
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dev->last_context, lock.context);
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}
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}
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#endif
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if (!ret) {
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if (lock.flags & _DRM_LOCK_READY) {
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/* Wait for space in DMA/FIFO */
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}
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if (lock.flags & _DRM_LOCK_QUIESCENT) {
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/* Make hardware quiescent */
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#if 0
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i810_quiescent(dev);
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#endif
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}
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}
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#if 0
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DRM_ERROR("pid = %5d, old counter = %5ld\n",
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current->pid, current->counter);
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#endif
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if (lock.context != i810_res_ctx.handle) {
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current->counter = 5;
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current->priority = DEF_PRIORITY/4;
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}
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#if 0
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while (current->counter > 25)
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current->counter >>= 1; /* decrease time slice */
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DRM_ERROR("pid = %5d, new counter = %5ld\n",
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current->pid, current->counter);
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#endif
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DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
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#if DRM_DMA_HISTOGRAM
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@ -694,7 +633,7 @@ int i810_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
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|||
if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
|
||||
atomic_inc(&dev->total_contends);
|
||||
drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
|
||||
i810_dma_schedule(dev, 1);
|
||||
/* i810_dma_schedule(dev, 1); */
|
||||
if (!dev->context_flag) {
|
||||
if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
|
||||
DRM_KERNEL_CONTEXT)) {
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ MODVERSIONS := $(shell \
|
|||
|
||||
# **** End of SMP/MODVERSIONS detection
|
||||
|
||||
MODS= gamma.o tdfx.o mga.o r128.o
|
||||
MODS= gamma.o tdfx.o mga.o r128.o i810.o
|
||||
LIBS= libdrm.a
|
||||
PROGS= drmstat
|
||||
|
||||
|
|
@ -77,6 +77,9 @@ MGAHEADERS= mga_drv.h $(DRMHEADERS)
|
|||
R128OBJS= r128_drv.o r128_context.o
|
||||
R128HEADERS= r128_drv.h $(DRMHEADERS)
|
||||
|
||||
I810OBJS= i810_drv.o i810_context.o
|
||||
I810HEADERS= i810_drv.h $(DRMHEADERS)
|
||||
|
||||
PROGOBJS= drmstat.po xf86drm.po xf86drmHash.po xf86drmRandom.po sigio.po
|
||||
PROGHEADERS= xf86drm.h $(DRMHEADERS)
|
||||
|
||||
|
|
@ -121,6 +124,9 @@ mga.o: $(MGAOBJS) $(LIBS)
|
|||
r128.o: $(R128OBJS) $(LIBS)
|
||||
$(LD) -r $^ -o $@
|
||||
|
||||
i810.o: $(I810OBJS) $(LIBS)
|
||||
$(LD) -r $^ -o $@
|
||||
|
||||
drmstat: $(PROGOBJS)
|
||||
$(CC) $(PRGCFLAGS) $^ $(PRGLIBS) -o $@
|
||||
|
||||
|
|
|
|||
|
|
@ -269,7 +269,7 @@ drm_agp_head_t *drm_agp_init(void)
|
|||
*fill->f = (drm_agp_func_u)get_module_symbol(NULL, n);
|
||||
#endif
|
||||
*fill->f = (drm_agp_func_u)get_module_symbol(NULL, n);
|
||||
DRM_DEBUG("%s resolves to 0x%08lx\n", n, (*fill->f).address);
|
||||
printk("%s resolves to 0x%08lx\n", n, (*fill->f).address);
|
||||
if (!(*fill->f).address) agp_available = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,19 +32,19 @@
|
|||
|
||||
#define __NO_VERSION__
|
||||
#include "drmP.h"
|
||||
#include "mga_drv.h"
|
||||
#include "i810_drv.h"
|
||||
|
||||
#include <linux/interrupt.h> /* For task queue support */
|
||||
|
||||
#define MGA_REG(reg) 0 /* for now */
|
||||
#define MGA_BASE(reg) ((unsigned long) \
|
||||
dev->maplist[MGA_REG(reg)]->handle)
|
||||
#define MGA_ADDR(reg) (MGA_BASE(reg) + MGA_OFF(reg))
|
||||
#define MGA_DEREF(reg) *(__volatile__ int *)MGA_ADDR(reg)
|
||||
#define MGA_READ(reg) MGA_DEREF(reg)
|
||||
#define MGA_WRITE(reg,val) do { MGA_DEREF(reg) = val; } while (0)
|
||||
#define I810_REG(reg) 0 /* for now */
|
||||
#define I810_BASE(reg) ((unsigned long) \
|
||||
dev->maplist[I810_REG(reg)]->handle)
|
||||
#define I810_ADDR(reg) (I810_BASE(reg) + I810_OFF(reg))
|
||||
#define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg)
|
||||
#define I810_READ(reg) I810_DEREF(reg)
|
||||
#define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0)
|
||||
|
||||
typedef _mga_primary_buffer {
|
||||
typedef _i810_primary_buffer {
|
||||
u32 *head;
|
||||
u32 *dma_ptr;
|
||||
u8 tempIndex[4];
|
||||
|
|
@ -52,9 +52,9 @@ typedef _mga_primary_buffer {
|
|||
int num_dwords;
|
||||
int max_dwords;
|
||||
unsigned long phys_head;
|
||||
} mgaPrimBuf;
|
||||
} i810PrimBuf;
|
||||
|
||||
static mgaPrimBuf buffer;
|
||||
static i810PrimBuf buffer;
|
||||
typedef enum {
|
||||
TT_GENERAL,
|
||||
TT_BLIT,
|
||||
|
|
@ -83,7 +83,7 @@ buffer.num_dwords += 5; \
|
|||
|
||||
#define CHECK_OVERFLOW(length) do { \
|
||||
if((buffer.max_dwords - buffer.num_dwords) < length) { \
|
||||
mga_prim_overflow(); \
|
||||
i810_prim_overflow(); \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
|
|
@ -96,14 +96,14 @@ static inline void i810_dma_dispatch(drm_device_t *dev, unsigned long address,
|
|||
int use_agp = PDEA_pagpxfer_enable;
|
||||
|
||||
CHECK_OVERFLOW(10);
|
||||
DMAOUTREG(MGAREG_DMAPAD, 0);
|
||||
DMAOUTREG(MGAREG_DMAPAD, 0);
|
||||
DMAOUTREG(MGAREG_SECADDRESS, address | transferType);
|
||||
DMAOUTREG(MGAREG_SECEND, (address + length) | use_agp);
|
||||
DMAOUTREG(MGAREG_DMAPAD, 0);
|
||||
DMAOUTREG(MGAREG_DMAPAD, 0);
|
||||
DMAOUTREG(MGAREG_DWGSYNC, 0);
|
||||
DMAOUTREG(MGAREG_SOFTRAP, 0);
|
||||
DMAOUTREG(I810REG_DMAPAD, 0);
|
||||
DMAOUTREG(I810REG_DMAPAD, 0);
|
||||
DMAOUTREG(I810REG_SECADDRESS, address | transferType);
|
||||
DMAOUTREG(I810REG_SECEND, (address + length) | use_agp);
|
||||
DMAOUTREG(I810REG_DMAPAD, 0);
|
||||
DMAOUTREG(I810REG_DMAPAD, 0);
|
||||
DMAOUTREG(I810REG_DWGSYNC, 0);
|
||||
DMAOUTREG(I810REG_SOFTRAP, 0);
|
||||
/* Needs to write out to PRIMEND */
|
||||
}
|
||||
|
||||
|
|
@ -159,7 +159,7 @@ static void i810_dma_service(int irq, void *device, struct pt_regs *regs)
|
|||
GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */
|
||||
GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8);
|
||||
GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001);
|
||||
if (mga_dma_is_ready(dev)) {
|
||||
if (i810_dma_is_ready(dev)) {
|
||||
/* Free previous buffer */
|
||||
if (test_and_set_bit(0, &dev->dma_flag)) {
|
||||
atomic_inc(&dma->total_missed_free);
|
||||
|
|
@ -227,7 +227,7 @@ static int i810_do_dma(drm_device_t *dev, int locked)
|
|||
return 0;
|
||||
}
|
||||
|
||||
if (!mga_dma_is_ready(dev)) {
|
||||
if (!i810_dma_is_ready(dev)) {
|
||||
clear_bit(0, &dev->dma_flag);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
|
@ -273,7 +273,7 @@ static int i810_do_dma(drm_device_t *dev, int locked)
|
|||
buf->time_dispatched = get_cycles();
|
||||
#endif
|
||||
|
||||
mga_dma_dispatch(dev, address, length);
|
||||
i810_dma_dispatch(dev, address, length);
|
||||
drm_free_buffer(dev, dma->this_buffer);
|
||||
dma->this_buffer = buf;
|
||||
|
||||
|
|
@ -346,14 +346,14 @@ again:
|
|||
or the DMA engine wasn't ready. Try
|
||||
again. */
|
||||
atomic_inc(&dma->total_tried);
|
||||
if (!(retcode = mga_do_dma(dev, locked))) {
|
||||
if (!(retcode = i810_do_dma(dev, locked))) {
|
||||
atomic_inc(&dma->total_hit);
|
||||
++processed;
|
||||
}
|
||||
} else {
|
||||
do {
|
||||
next = drm_select_queue(dev,
|
||||
mga_dma_schedule_timer_wrapper);
|
||||
i810_dma_schedule_timer_wrapper);
|
||||
if (next >= 0) {
|
||||
q = dev->queuelist[next];
|
||||
buf = drm_waitlist_get(&q->waitlist);
|
||||
|
|
@ -366,7 +366,7 @@ again:
|
|||
}
|
||||
} while (next >= 0 && !dma->next_buffer);
|
||||
if (dma->next_buffer) {
|
||||
if (!(retcode = mga_do_dma(dev, locked))) {
|
||||
if (!(retcode = i810_do_dma(dev, locked))) {
|
||||
++processed;
|
||||
}
|
||||
}
|
||||
|
|
@ -375,9 +375,9 @@ again:
|
|||
if (--expire) {
|
||||
if (missed != atomic_read(&dma->total_missed_sched)) {
|
||||
atomic_inc(&dma->total_lost);
|
||||
if (mga_dma_is_ready(dev)) goto again;
|
||||
if (i810_dma_is_ready(dev)) goto again;
|
||||
}
|
||||
if (processed && mga_dma_is_ready(dev)) {
|
||||
if (processed && i810_dma_is_ready(dev)) {
|
||||
atomic_inc(&dma->total_lost);
|
||||
processed = 0;
|
||||
goto again;
|
||||
|
|
@ -506,7 +506,7 @@ static int i810_dma_priority(drm_device_t *dev, drm_dma_t *d)
|
|||
buf->time_queued = get_cycles();
|
||||
buf->time_dispatched = buf->time_queued;
|
||||
#endif
|
||||
mga_dma_dispatch(dev, address, length);
|
||||
i810_dma_dispatch(dev, address, length);
|
||||
atomic_add(length, &dma->total_bytes);
|
||||
atomic_inc(&dma->total_dmas);
|
||||
|
||||
|
|
@ -519,7 +519,7 @@ static int i810_dma_priority(drm_device_t *dev, drm_dma_t *d)
|
|||
|
||||
cleanup:
|
||||
if (last_buf) {
|
||||
mga_dma_ready(dev);
|
||||
i810_dma_ready(dev);
|
||||
drm_free_buffer(dev, last_buf);
|
||||
}
|
||||
|
||||
|
|
@ -551,7 +551,7 @@ static int i810_dma_send_buffers(drm_device_t *dev, drm_dma_t *d)
|
|||
return retcode;
|
||||
}
|
||||
|
||||
mga_dma_schedule(dev, 0);
|
||||
i810_dma_schedule(dev, 0);
|
||||
|
||||
if (d->flags & _DRM_DMA_BLOCK) {
|
||||
DRM_DEBUG("%d waiting\n", current->pid);
|
||||
|
|
@ -621,9 +621,9 @@ int i810_dma(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
|
||||
if (d.send_count) {
|
||||
if (d.flags & _DRM_DMA_PRIORITY)
|
||||
retcode = mga_dma_priority(dev, &d);
|
||||
retcode = i810_dma_priority(dev, &d);
|
||||
else
|
||||
retcode = mga_dma_send_buffers(dev, &d);
|
||||
retcode = i810_dma_send_buffers(dev, &d);
|
||||
}
|
||||
|
||||
d.granted_count = 0;
|
||||
|
|
@ -665,16 +665,16 @@ int i810_irq_install(drm_device_t *dev, int irq)
|
|||
|
||||
dev->tq.next = NULL;
|
||||
dev->tq.sync = 0;
|
||||
dev->tq.routine = mga_dma_schedule_tq_wrapper;
|
||||
dev->tq.routine = i810_dma_schedule_tq_wrapper;
|
||||
dev->tq.data = dev;
|
||||
|
||||
|
||||
/* Before installing handler */
|
||||
MGA_WRITE(MGAREG_IEN, 0);
|
||||
I810_WRITE(I810REG_IEN, 0);
|
||||
|
||||
/* Install handler */
|
||||
if ((retcode = request_irq(dev->irq,
|
||||
mga_dma_service,
|
||||
i810_dma_service,
|
||||
0,
|
||||
dev->devname,
|
||||
dev))) {
|
||||
|
|
@ -685,7 +685,7 @@ int i810_irq_install(drm_device_t *dev, int irq)
|
|||
}
|
||||
|
||||
/* After installing handler */
|
||||
MGA_WRITE(MGAREG_IEN, 0x00000001);
|
||||
I810_WRITE(I810REG_IEN, 0x00000001);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -702,7 +702,7 @@ int i810_irq_uninstall(drm_device_t *dev)
|
|||
|
||||
DRM_DEBUG("%d\n", irq);
|
||||
|
||||
MGA_WRITE(MGAREG_IEN, 0);
|
||||
I810_WRITE(I810REG_IEN, 0);
|
||||
free_irq(irq, dev);
|
||||
|
||||
return 0;
|
||||
|
|
@ -721,11 +721,11 @@ int i810_control(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
|
||||
switch (ctl.func) {
|
||||
case DRM_INST_HANDLER:
|
||||
if ((retcode = mga_irq_install(dev, ctl.irq)))
|
||||
if ((retcode = i810_irq_install(dev, ctl.irq)))
|
||||
return retcode;
|
||||
break;
|
||||
case DRM_UNINST_HANDLER:
|
||||
if ((retcode = mga_irq_uninstall(dev)))
|
||||
if ((retcode = i810_irq_uninstall(dev)))
|
||||
return retcode;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -812,9 +812,9 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
|
||||
if (!ret) {
|
||||
if (lock.flags & _DRM_LOCK_READY)
|
||||
mga_dma_ready(dev);
|
||||
i810_dma_ready(dev);
|
||||
if (lock.flags & _DRM_LOCK_QUIESCENT)
|
||||
mga_dma_quiescent(dev);
|
||||
i810_dma_quiescent(dev);
|
||||
}
|
||||
DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ EXPORT_SYMBOL(i810_init);
|
|||
EXPORT_SYMBOL(i810_cleanup);
|
||||
|
||||
#define I810_NAME "i810"
|
||||
#define I810_DESC "Matrox g200/g400"
|
||||
#define I810_DESC "Intel i810"
|
||||
#define I810_DATE "19991213"
|
||||
#define I810_MAJOR 0
|
||||
#define I810_MINOR 0
|
||||
|
|
@ -71,14 +71,19 @@ static drm_ioctl_desc_t i810_ioctls[] = {
|
|||
[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 },
|
||||
#if 0
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { i810_control, 1, 1 },
|
||||
#endif
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 },
|
||||
|
||||
#if 0
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { i810_addbufs, 1, 1 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { i810_markbufs, 1, 1 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { i810_infobufs, 1, 0 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { i810_mapbufs, 1, 0 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { i810_freebufs, 1, 0 },
|
||||
#endif
|
||||
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { i810_addctx, 1, 1 },
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { i810_rmctx, 1, 1 },
|
||||
|
|
@ -99,7 +104,7 @@ static drm_ioctl_desc_t i810_ioctls[] = {
|
|||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire, 1, 1},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release, 1, 1},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable, 1, 1},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 1},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 0},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1},
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_unbind, 1, 1},
|
||||
|
|
@ -228,7 +233,7 @@ static int i810_takedown(drm_device_t *dev)
|
|||
|
||||
DRM_DEBUG("\n");
|
||||
|
||||
if (dev->irq) i810_irq_uninstall(dev);
|
||||
/* if (dev->irq) i810_irq_uninstall(dev); */
|
||||
|
||||
down(&dev->struct_sem);
|
||||
del_timer(&dev->timer);
|
||||
|
|
@ -552,33 +557,7 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
lock.context, current->pid, dev->lock.hw_lock->lock,
|
||||
lock.flags);
|
||||
|
||||
#if 0
|
||||
/* dev->queue_count == 0 right now for
|
||||
i810. FIXME? */
|
||||
if (lock.context < 0 || lock.context >= dev->queue_count)
|
||||
return -EINVAL;
|
||||
#endif
|
||||
|
||||
if (!ret) {
|
||||
#if 0
|
||||
if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)
|
||||
!= lock.context) {
|
||||
long j = jiffies - dev->lock.lock_time;
|
||||
|
||||
if (lock.context == i810_res_ctx.handle &&
|
||||
j >= 0 && j < DRM_LOCK_SLICE) {
|
||||
/* Can't take lock if we just had it and
|
||||
there is contention. */
|
||||
DRM_DEBUG("%d (pid %d) delayed j=%d dev=%d jiffies=%d\n",
|
||||
lock.context, current->pid, j,
|
||||
dev->lock.lock_time, jiffies);
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
current->policy |= SCHED_YIELD;
|
||||
schedule_timeout(DRM_LOCK_SLICE-j);
|
||||
DRM_DEBUG("jiffies=%d\n", jiffies);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
add_wait_queue(&dev->lock.lock_queue, &entry);
|
||||
for (;;) {
|
||||
if (!dev->lock.hw_lock) {
|
||||
|
|
@ -597,9 +576,7 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
/* Contention */
|
||||
atomic_inc(&dev->total_sleeps);
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
#if 1
|
||||
current->policy |= SCHED_YIELD;
|
||||
#endif
|
||||
schedule();
|
||||
if (signal_pending(current)) {
|
||||
ret = -ERESTARTSYS;
|
||||
|
|
@ -610,58 +587,20 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
remove_wait_queue(&dev->lock.lock_queue, &entry);
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (!ret && dev->last_context != lock.context &&
|
||||
lock.context != i810_res_ctx.handle &&
|
||||
dev->last_context != i810_res_ctx.handle) {
|
||||
add_wait_queue(&dev->context_wait, &entry);
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
/* PRE: dev->last_context != lock.context */
|
||||
i810_context_switch(dev, dev->last_context, lock.context);
|
||||
/* POST: we will wait for the context
|
||||
switch and will dispatch on a later call
|
||||
when dev->last_context == lock.context
|
||||
NOTE WE HOLD THE LOCK THROUGHOUT THIS
|
||||
TIME! */
|
||||
current->policy |= SCHED_YIELD;
|
||||
schedule();
|
||||
current->state = TASK_RUNNING;
|
||||
remove_wait_queue(&dev->context_wait, &entry);
|
||||
if (signal_pending(current)) {
|
||||
ret = -EINTR;
|
||||
} else if (dev->last_context != lock.context) {
|
||||
DRM_ERROR("Context mismatch: %d %d\n",
|
||||
dev->last_context, lock.context);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (!ret) {
|
||||
if (lock.flags & _DRM_LOCK_READY) {
|
||||
/* Wait for space in DMA/FIFO */
|
||||
}
|
||||
if (lock.flags & _DRM_LOCK_QUIESCENT) {
|
||||
/* Make hardware quiescent */
|
||||
#if 0
|
||||
i810_quiescent(dev);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
DRM_ERROR("pid = %5d, old counter = %5ld\n",
|
||||
current->pid, current->counter);
|
||||
#endif
|
||||
if (lock.context != i810_res_ctx.handle) {
|
||||
current->counter = 5;
|
||||
current->priority = DEF_PRIORITY/4;
|
||||
}
|
||||
#if 0
|
||||
while (current->counter > 25)
|
||||
current->counter >>= 1; /* decrease time slice */
|
||||
DRM_ERROR("pid = %5d, new counter = %5ld\n",
|
||||
current->pid, current->counter);
|
||||
#endif
|
||||
|
||||
DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
|
||||
|
||||
#if DRM_DMA_HISTOGRAM
|
||||
|
|
@ -694,7 +633,7 @@ int i810_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
|
||||
atomic_inc(&dev->total_contends);
|
||||
drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
|
||||
i810_dma_schedule(dev, 1);
|
||||
/* i810_dma_schedule(dev, 1); */
|
||||
if (!dev->context_flag) {
|
||||
if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
|
||||
DRM_KERNEL_CONTEXT)) {
|
||||
|
|
|
|||
|
|
@ -390,13 +390,15 @@ int drm_free_agp(agp_memory *handle, int pages)
|
|||
int drm_bind_agp(agp_memory *handle, unsigned int start)
|
||||
{
|
||||
int retcode = -EINVAL;
|
||||
|
||||
|
||||
printk("drm_bind_agp called\n");
|
||||
if (!handle) {
|
||||
DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
|
||||
"Attempt to bind NULL AGP handle\n");
|
||||
return retcode;
|
||||
}
|
||||
|
||||
printk("drm_agp.bind_memory : %p\n", drm_agp.bind_memory);
|
||||
if (drm_agp.bind_memory) {
|
||||
if (!(retcode = (*drm_agp.bind_memory)(handle, start))) {
|
||||
spin_lock(&drm_mem_lock);
|
||||
|
|
@ -404,6 +406,7 @@ int drm_bind_agp(agp_memory *handle, unsigned int start)
|
|||
drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated
|
||||
+= handle->page_count << PAGE_SHIFT;
|
||||
spin_unlock(&drm_mem_lock);
|
||||
printk("drm_agp.bind_memory: retcode %d\n", retcode);
|
||||
return retcode;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue