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https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-04-27 07:20:40 +02:00
white space changes to align with kernel
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parent
7e0f883501
commit
3306abbde7
6 changed files with 40 additions and 40 deletions
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@ -217,25 +217,25 @@ typedef struct drm_r128_sarea {
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#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
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#define DRM_IOCTL_R128_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
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#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
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typedef struct drm_r128_init {
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enum {
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R128_INIT_CCE = 0x01,
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R128_CLEANUP_CCE = 0x02
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} func;
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typedef struct drm_r128_init {
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enum {
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R128_INIT_CCE = 0x01,
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R128_CLEANUP_CCE = 0x02
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} func;
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#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
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int sarea_priv_offset;
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#else
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unsigned long sarea_priv_offset;
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#endif
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int is_pci;
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int cce_mode;
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int cce_secure;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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int sarea_priv_offset;
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#else
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unsigned long sarea_priv_offset;
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#endif
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int is_pci;
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int cce_mode;
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int cce_secure;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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@ -915,7 +915,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
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DRM_DEBUG( "\n" );
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count = depth->n;
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if (count>4096 || count<=0)
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if (count > 4096 || count <= 0)
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return -EMSGSIZE;
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if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
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@ -424,7 +424,7 @@ typedef struct {
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#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
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#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
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#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
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typedef struct drm_radeon_init {
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enum {
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RADEON_INIT_CP = 0x01,
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@ -217,25 +217,25 @@ typedef struct drm_r128_sarea {
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#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
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#define DRM_IOCTL_R128_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
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#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
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typedef struct drm_r128_init {
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enum {
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R128_INIT_CCE = 0x01,
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R128_CLEANUP_CCE = 0x02
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} func;
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typedef struct drm_r128_init {
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enum {
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R128_INIT_CCE = 0x01,
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R128_CLEANUP_CCE = 0x02
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} func;
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#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
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int sarea_priv_offset;
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#else
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unsigned long sarea_priv_offset;
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#endif
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int is_pci;
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int cce_mode;
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int cce_secure;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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int sarea_priv_offset;
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#else
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unsigned long sarea_priv_offset;
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#endif
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int is_pci;
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int cce_mode;
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int cce_secure;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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@ -915,7 +915,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
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DRM_DEBUG( "\n" );
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count = depth->n;
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if (count>4096 || count<=0)
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if (count > 4096 || count <= 0)
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return -EMSGSIZE;
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if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
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@ -424,7 +424,7 @@ typedef struct {
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#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
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#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
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#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
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typedef struct drm_radeon_init {
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enum {
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RADEON_INIT_CP = 0x01,
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