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Don't activate blend fallbacks unless blending is enabled

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This commit is contained in:
Keith Whitwell 2003-06-09 23:11:23 +00:00
parent 1a2bb43329
commit 1062b9930f
2 changed files with 10 additions and 0 deletions
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5
shared-core/radeon_state.c
View file

@ -292,6 +292,9 @@ static struct {
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
};
@ -1168,6 +1171,8 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
}
printk("Upload to %x\n", tex->offset);
/* Dispatch the indirect buffer.
*/
buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);

5
shared/radeon_state.c
View file

@ -292,6 +292,9 @@ static struct {
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
};
@ -1168,6 +1171,8 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
}
printk("Upload to %x\n", tex->offset);
/* Dispatch the indirect buffer.
*/
buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);