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don't draw if window is unmapped, other updates (Jeff Hartmann)

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This commit is contained in:
Brian Paul 2000-06-08 17:13:48 +00:00
parent 569da5a42e
commit 0dc99dc4b9
1 changed files with 579 additions and 586 deletions
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213
linux/mga_state.c
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@ -24,8 +24,8 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
* *
* Authors: Jeff Hartmann <jhartmann@valinux.com> * Authors: Jeff Hartmann <jhartmann@precisioninsight.com>
* Keith Whitwell <keithw@valinux.com> * Keith Whitwell <keithw@precisioninsight.com>
* *
*/ */
@ -46,7 +46,7 @@ static void mgaEmitClipRect( drm_mga_private_t *dev_priv,
PRIMGETPTR(dev_priv); PRIMGETPTR(dev_priv);
/* Force reset of dwgctl (eliminates clip disable) */ /* Force reset of dwgctl (eliminates clip disable) */
#if 1 #if 0
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DWGSYNC, 0); PRIMOUTREG(MGAREG_DWGSYNC, 0);
PRIMOUTREG(MGAREG_DWGSYNC, 0); PRIMOUTREG(MGAREG_DWGSYNC, 0);
@ -147,7 +147,7 @@ static void mgaG400EmitTex0( drm_mga_private_t *dev_priv )
/* This takes a max of 30 dwords */ /* This takes a max of 30 dwords */
PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] ); PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
@ -195,7 +195,8 @@ static void mgaG400EmitTex1( drm_mga_private_t *dev_priv )
/* This takes 25 dwords */ /* This takes 25 dwords */
PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | TMC_map1_enable ); PRIMOUTREG(MGAREG_TEXCTL2,
regs[MGA_TEXREG_CTL2] | TMC_map1_enable | 0x00008000);
PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
@ -218,40 +219,12 @@ static void mgaG400EmitTex1( drm_mga_private_t *dev_priv )
PRIMOUTREG(0x2d00 + 60 * 4, regs[MGA_TEXREG_HEIGHT] | 0x40); PRIMOUTREG(0x2d00 + 60 * 4, regs[MGA_TEXREG_HEIGHT] | 0x40);
PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] ); PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
PRIMADVANCE( dev_priv );
}
/* Required when switching from multitexturing to single texturing.
*/
static void mgaG400EmitTexFlush( drm_mga_private_t *dev_priv )
{
PRIMLOCALS;
DRM_DEBUG("%s\n", __FUNCTION__);
PRIMGETPTR( dev_priv );
/* This takes 15 dwords */
PRIMOUTREG( MGAREG_YDST, 0 );
PRIMOUTREG( MGAREG_FXLEFT, 0 );
PRIMOUTREG( MGAREG_FXRIGHT, 1 );
PRIMOUTREG( MGAREG_DWGCTL, MGA_FLUSH_CMD );
PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 1 );
PRIMOUTREG( MGAREG_DMAPAD, 0 );
PRIMOUTREG( MGAREG_DWGSYNC, 0x7000 );
PRIMOUTREG( MGAREG_DMAPAD, 0 );
PRIMOUTREG( MGAREG_TEXCTL2, 0 );
PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0 );
PRIMOUTREG( MGAREG_TEXCTL2, 0x80 );
PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0 );
PRIMADVANCE(dev_priv); PRIMADVANCE(dev_priv);
} }
#define EMIT_PIPE 50
static void mgaG400EmitPipe(drm_mga_private_t * dev_priv) static void mgaG400EmitPipe(drm_mga_private_t * dev_priv)
{ {
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@ -262,25 +235,48 @@ static void mgaG400EmitPipe( drm_mga_private_t *dev_priv )
PRIMGETPTR(dev_priv); PRIMGETPTR(dev_priv);
/* This takes 30 dwords */ /* This takes 50 dwords */
/* Establish vertex size. /* Establish vertex size.
*/ */
if (pipe & MGA_T2) {
PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend); PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend);
PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0);
if (pipe & MGA_T2) {
PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09); PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000);
} else { } else {
PRIMOUTREG( MGAREG_WIADDR2, WIA_wmode_suspend ); if (dev_priv->WarpPipe & MGA_T2) {
/* Flush the WARP pipe */
PRIMOUTREG(MGAREG_YDST, 0);
PRIMOUTREG(MGAREG_FXLEFT, 0);
PRIMOUTREG(MGAREG_FXRIGHT, 1);
PRIMOUTREG(MGAREG_DWGCTL, MGA_FLUSH_CMD);
PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 1);
PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DWGSYNC, 0x7000);
PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_TEXCTL2, 0 | 0x00008000);
PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
PRIMOUTREG(MGAREG_TEXCTL2, 0x80 | 0x00008000);
PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
}
PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807); PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
@ -307,8 +303,9 @@ static void mgaG400EmitPipe( drm_mga_private_t *dev_priv )
PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
PRIMOUTREG( MGAREG_WIADDR2, (u32)(dev_priv->WarpIndex[pipe].phys_addr | PRIMOUTREG(MGAREG_WIADDR2,
WIA_wmode_start | WIA_wagp_agp) ); (u32) (dev_priv->WarpIndex[pipe].
phys_addr | WIA_wmode_start | WIA_wagp_agp));
PRIMADVANCE(dev_priv); PRIMADVANCE(dev_priv);
} }
@ -337,8 +334,9 @@ static void mgaG200EmitPipe( drm_mga_private_t *dev_priv )
PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
PRIMOUTREG( MGAREG_WIADDR, (u32)(dev_priv->WarpIndex[pipe].phys_addr | PRIMOUTREG(MGAREG_WIADDR,
WIA_wmode_start | WIA_wagp_agp) ); (u32) (dev_priv->WarpIndex[pipe].
phys_addr | WIA_wmode_start | WIA_wagp_agp));
PRIMADVANCE(dev_priv); PRIMADVANCE(dev_priv);
} }
@ -353,9 +351,6 @@ static void mgaEmitState( drm_mga_private_t *dev_priv )
int multitex = sarea_priv->WarpPipe & MGA_T2; int multitex = sarea_priv->WarpPipe & MGA_T2;
if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
if ((dev_priv->WarpPipe & MGA_T2) && !multitex) {
mgaG400EmitTexFlush( dev_priv );
}
mgaG400EmitPipe(dev_priv); mgaG400EmitPipe(dev_priv);
dev_priv->WarpPipe = sarea_priv->WarpPipe; dev_priv->WarpPipe = sarea_priv->WarpPipe;
} }
@ -416,8 +411,7 @@ static int mgaVerifyContext(drm_mga_private_t *dev_priv )
/* Disallow texture reads from PCI space. /* Disallow texture reads from PCI space.
*/ */
static int mgaVerifyTex(drm_mga_private_t *dev_priv, static int mgaVerifyTex(drm_mga_private_t * dev_priv, int unit)
int unit)
{ {
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@ -451,16 +445,13 @@ static int mgaVerifyState( drm_mga_private_t *dev_priv )
if (dirty & MGA_UPLOAD_TEX0) if (dirty & MGA_UPLOAD_TEX0)
rv |= mgaVerifyTex(dev_priv, 0); rv |= mgaVerifyTex(dev_priv, 0);
if (dev_priv->chipset == MGA_CARD_TYPE_G400) if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
{
if (dirty & MGA_UPLOAD_TEX1) if (dirty & MGA_UPLOAD_TEX1)
rv |= mgaVerifyTex(dev_priv, 1); rv |= mgaVerifyTex(dev_priv, 1);
if (dirty & MGA_UPLOAD_PIPE) if (dirty & MGA_UPLOAD_PIPE)
rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES); rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES);
} } else {
else
{
if (dirty & MGA_UPLOAD_PIPE) if (dirty & MGA_UPLOAD_PIPE)
rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES); rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES);
} }
@ -490,8 +481,7 @@ static int mgaVerifyIload( drm_mga_private_t *dev_priv,
static void mga_dma_dispatch_tex_blit(drm_device_t * dev, static void mga_dma_dispatch_tex_blit(drm_device_t * dev,
unsigned long bus_address, unsigned long bus_address,
int length, int length, unsigned int destOrg)
unsigned int destOrg )
{ {
drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_private_t *dev_priv = dev->dev_private;
int use_agp = PDEA_pagpxfer_enable | 0x00000001; int use_agp = PDEA_pagpxfer_enable | 0x00000001;
@ -527,8 +517,7 @@ static void mga_dma_dispatch_tex_blit( drm_device_t *dev,
PRIMADVANCE(dev_priv); PRIMADVANCE(dev_priv);
} }
static void mga_dma_dispatch_vertex(drm_device_t *dev, static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
drm_buf_t *buf)
{ {
drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@ -547,22 +536,14 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
sarea_priv->nbox, sarea_priv->dirty); sarea_priv->nbox, sarea_priv->dirty);
DRM_DEBUG("used : %d, total : %d\n", buf->used, buf->total); DRM_DEBUG("used : %d, total : %d\n", buf->used, buf->total);
if(sarea_priv->WarpPipe & MGA_T2) {
if ((buf->used/4) % 10)
DRM_DEBUG("Multitex Buf is not aligned properly!!!\n");
} else {
if ((buf->used/4) % 8)
DRM_DEBUG("Buf is not aligned properly!!!\n");
}
if (buf->used) { if (buf->used) {
/* WARNING: if you change any of the state functions verify /* WARNING: if you change any of the state functions verify
* these numbers (Overestimating this doesn't hurt). * these numbers (Overestimating this doesn't hurt).
*/ */
buf_priv->dispatched = 1; buf_priv->dispatched = 1;
primary_needed = (30+15+15+30+25+ primary_needed = (50 + 15 + 15 + 30 + 25 +
10 + 10 + 15 * MGA_NR_SAREA_CLIPRECTS);
15 * MGA_NR_SAREA_CLIPRECTS);
PRIM_OVERFLOW(dev, dev_priv, primary_needed); PRIM_OVERFLOW(dev, dev_priv, primary_needed);
mgaEmitState(dev_priv); mgaEmitState(dev_priv);
@ -593,7 +574,8 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
} }
if (buf_priv->discard) { if (buf_priv->discard) {
if (buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv); if (buf_priv->dispatched == 1)
AGEBUF(dev_priv, buf_priv);
buf_priv->dispatched = 0; buf_priv->dispatched = 0;
mga_freelist_put(dev, buf); mga_freelist_put(dev, buf);
} }
@ -604,8 +586,7 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
static void mga_dma_dispatch_indices(drm_device_t * dev, static void mga_dma_dispatch_indices(drm_device_t * dev,
drm_buf_t * buf, drm_buf_t * buf,
unsigned int start, unsigned int start, unsigned int end)
unsigned int end)
{ {
drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@ -627,9 +608,8 @@ static void mga_dma_dispatch_indices(drm_device_t *dev,
* these numbers (Overestimating this doesn't hurt). * these numbers (Overestimating this doesn't hurt).
*/ */
buf_priv->dispatched = 1; buf_priv->dispatched = 1;
primary_needed = (25+15+30+25+ primary_needed = (50 + 15 + 15 + 30 + 25 +
10 + 10 + 15 * MGA_NR_SAREA_CLIPRECTS);
15 * MGA_NR_SAREA_CLIPRECTS);
PRIM_OVERFLOW(dev, dev_priv, primary_needed); PRIM_OVERFLOW(dev, dev_priv, primary_needed);
mgaEmitState(dev_priv); mgaEmitState(dev_priv);
@ -660,7 +640,8 @@ static void mga_dma_dispatch_indices(drm_device_t *dev,
} while (++i < sarea_priv->nbox); } while (++i < sarea_priv->nbox);
} }
if (buf_priv->discard) { if (buf_priv->discard) {
if (buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv); if (buf_priv->dispatched == 1)
AGEBUF(dev_priv, buf_priv);
buf_priv->dispatched = 0; buf_priv->dispatched = 0;
mga_freelist_put(dev, buf); mga_freelist_put(dev, buf);
} }
@ -688,7 +669,8 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
cmd = MGA_CLEAR_CMD | DC_atype_rstr; cmd = MGA_CLEAR_CMD | DC_atype_rstr;
primary_needed = nbox * 70; primary_needed = nbox * 70;
if (primary_needed == 0) primary_needed = 70; if (primary_needed == 0)
primary_needed = 70;
PRIM_OVERFLOW(dev, dev_priv, primary_needed); PRIM_OVERFLOW(dev, dev_priv, primary_needed);
PRIMGETPTR(dev_priv); PRIMGETPTR(dev_priv);
@ -703,8 +685,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
DRM_DEBUG("clear front\n"); DRM_DEBUG("clear front\n");
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height); PRIMOUTREG(MGAREG_YDSTLEN,
PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1); (pbox[i].y1 << 16) | height);
PRIMOUTREG(MGAREG_FXBNDRY,
(pbox[i].x2 << 16) | pbox[i].x1);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_FCOL, clear_color); PRIMOUTREG(MGAREG_FCOL, clear_color);
@ -716,8 +700,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
DRM_DEBUG("clear back\n"); DRM_DEBUG("clear back\n");
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height ); PRIMOUTREG(MGAREG_YDSTLEN,
PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1 ); (pbox[i].y1 << 16) | height);
PRIMOUTREG(MGAREG_FXBNDRY,
(pbox[i].x2 << 16) | pbox[i].x1);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_FCOL, clear_color); PRIMOUTREG(MGAREG_FCOL, clear_color);
@ -729,8 +715,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
DRM_DEBUG("clear depth\n"); DRM_DEBUG("clear depth\n");
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height ); PRIMOUTREG(MGAREG_YDSTLEN,
PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1 ); (pbox[i].y1 << 16) | height);
PRIMOUTREG(MGAREG_FXBNDRY,
(pbox[i].x2 << 16) | pbox[i].x1);
PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0);
PRIMOUTREG(MGAREG_FCOL, clear_zval); PRIMOUTREG(MGAREG_FCOL, clear_zval);
@ -779,13 +767,14 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
unsigned int start = pbox[i].y1 * dev_priv->stride / 2; unsigned int start = pbox[i].y1 * dev_priv->stride / 2;
DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
pbox[i].x1, pbox[i].y1, pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);
pbox[i].x2, pbox[i].y2);
PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1); PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1);
PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1); PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1);
PRIMOUTREG( MGAREG_FXBNDRY, pbox[i].x1|((pbox[i].x2 - 1)<<16) ); PRIMOUTREG(MGAREG_FXBNDRY,
PRIMOUTREG( MGAREG_YDSTLEN+MGAREG_MGA_EXEC, (pbox[i].y1<<16)|h ); pbox[i].x1 | ((pbox[i].x2 - 1) << 16));
PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC,
(pbox[i].y1 << 16) | h);
} }
/* Force reset of DWGCTL */ /* Force reset of DWGCTL */
@ -802,7 +791,8 @@ int mga_clear_bufs(struct inode *inode, struct file *filp,
{ {
drm_file_t *priv = filp->private_data; drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev; drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; drm_mga_private_t *dev_priv =
(drm_mga_private_t *) dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_clear_t clear; drm_mga_clear_t clear;
@ -822,8 +812,7 @@ int mga_clear_bufs(struct inode *inode, struct file *filp,
*/ */
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
mga_dma_dispatch_clear(dev, clear.flags, mga_dma_dispatch_clear(dev, clear.flags,
clear.clear_color, clear.clear_color, clear.clear_depth);
clear.clear_depth );
PRIMUPDATE(dev_priv); PRIMUPDATE(dev_priv);
mga_flush_write_combine(); mga_flush_write_combine();
mga_dma_schedule(dev, 1); mga_dma_schedule(dev, 1);
@ -835,7 +824,8 @@ int mga_swap_bufs(struct inode *inode, struct file *filp,
{ {
drm_file_t *priv = filp->private_data; drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev; drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; drm_mga_private_t *dev_priv =
(drm_mga_private_t *) dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
DRM_DEBUG("%s\n", __FUNCTION__); DRM_DEBUG("%s\n", __FUNCTION__);
@ -852,7 +842,8 @@ int mga_swap_bufs(struct inode *inode, struct file *filp,
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
mga_dma_dispatch_swap(dev); mga_dma_dispatch_swap(dev);
PRIMUPDATE(dev_priv); PRIMUPDATE(dev_priv);
set_bit(MGA_BUF_SWAP_PENDING, &dev_priv->current_prim->buffer_status); set_bit(MGA_BUF_SWAP_PENDING,
&dev_priv->current_prim->buffer_status);
mga_flush_write_combine(); mga_flush_write_combine();
mga_dma_schedule(dev, 1); mga_dma_schedule(dev, 1);
return 0; return 0;
@ -864,7 +855,8 @@ int mga_iload(struct inode *inode, struct file *filp,
drm_file_t *priv = filp->private_data; drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev; drm_device_t *dev = priv->dev;
drm_device_dma_t *dma = dev->dma; drm_device_dma_t *dma = dev->dma;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; drm_mga_private_t *dev_priv =
(drm_mga_private_t *) dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_buf_t *buf; drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv; drm_mga_buf_priv_t *buf_priv;
@ -888,9 +880,7 @@ int mga_iload(struct inode *inode, struct file *filp,
bus_address, iload.length, iload.destOrg); bus_address, iload.length, iload.destOrg);
if (mgaVerifyIload(dev_priv, if (mgaVerifyIload(dev_priv,
bus_address, bus_address, iload.destOrg, iload.length)) {
iload.destOrg,
iload.length)) {
mga_freelist_put(dev, buf); mga_freelist_put(dev, buf);
return -EINVAL; return -EINVAL;
} }
@ -912,15 +902,16 @@ int mga_vertex(struct inode *inode, struct file *filp,
{ {
drm_file_t *priv = filp->private_data; drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev; drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; drm_mga_private_t *dev_priv =
(drm_mga_private_t *) dev->dev_private;
drm_device_dma_t *dma = dev->dma; drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf; drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv; drm_mga_buf_priv_t *buf_priv;
drm_mga_vertex_t vertex; drm_mga_vertex_t vertex;
DRM_DEBUG("%s\n", __FUNCTION__); DRM_DEBUG("%s\n", __FUNCTION__);
copy_from_user_ret(&vertex, (drm_mga_vertex_t *)arg, sizeof(vertex), copy_from_user_ret(&vertex, (drm_mga_vertex_t *) arg,
-EFAULT); sizeof(vertex), -EFAULT);
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
DRM_ERROR("mga_vertex called without lock held\n"); DRM_ERROR("mga_vertex called without lock held\n");
@ -937,7 +928,8 @@ int mga_vertex(struct inode *inode, struct file *filp,
if (!mgaVerifyState(dev_priv)) { if (!mgaVerifyState(dev_priv)) {
if (vertex.discard) { if (vertex.discard) {
if(buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv); if (buf_priv->dispatched == 1)
AGEBUF(dev_priv, buf_priv);
buf_priv->dispatched = 0; buf_priv->dispatched = 0;
mga_freelist_put(dev, buf); mga_freelist_put(dev, buf);
} }
@ -959,15 +951,16 @@ int mga_indices(struct inode *inode, struct file *filp,
{ {
drm_file_t *priv = filp->private_data; drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev; drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; drm_mga_private_t *dev_priv =
(drm_mga_private_t *) dev->dev_private;
drm_device_dma_t *dma = dev->dma; drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf; drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv; drm_mga_buf_priv_t *buf_priv;
drm_mga_indices_t indices; drm_mga_indices_t indices;
DRM_DEBUG("%s\n", __FUNCTION__); DRM_DEBUG("%s\n", __FUNCTION__);
copy_from_user_ret(&indices, (drm_mga_indices_t *)arg, sizeof(indices), copy_from_user_ret(&indices, (drm_mga_indices_t *) arg,
-EFAULT); sizeof(indices), -EFAULT);
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
DRM_ERROR("mga_indices called without lock held\n"); DRM_ERROR("mga_indices called without lock held\n");
@ -983,7 +976,8 @@ int mga_indices(struct inode *inode, struct file *filp,
if (!mgaVerifyState(dev_priv)) { if (!mgaVerifyState(dev_priv)) {
if (indices.discard) { if (indices.discard) {
if(buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv); if (buf_priv->dispatched == 1)
AGEBUF(dev_priv, buf_priv);
buf_priv->dispatched = 0; buf_priv->dispatched = 0;
mga_freelist_put(dev, buf); mga_freelist_put(dev, buf);
} }
@ -1008,16 +1002,13 @@ static int mga_dma_get_buffers(drm_device_t *dev, drm_dma_t *d)
for (i = d->granted_count; i < d->request_count; i++) { for (i = d->granted_count; i < d->request_count; i++) {
buf = mga_freelist_get(dev); buf = mga_freelist_get(dev);
if (!buf) break; if (!buf)
break;
buf->pid = current->pid; buf->pid = current->pid;
copy_to_user_ret(&d->request_indices[i], copy_to_user_ret(&d->request_indices[i],
&buf->idx, &buf->idx, sizeof(buf->idx), -EFAULT);
sizeof(buf->idx),
-EFAULT);
copy_to_user_ret(&d->request_sizes[i], copy_to_user_ret(&d->request_sizes[i],
&buf->total, &buf->total, sizeof(buf->total), -EFAULT);
sizeof(buf->total),
-EFAULT);
++d->granted_count; ++d->granted_count;
} }
return 0; return 0;
@ -1045,7 +1036,8 @@ int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
/* Please don't send us buffers. /* Please don't send us buffers.
*/ */
if (d.send_count != 0) { if (d.send_count != 0) {
DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_ERROR
("Process %d trying to send %d buffers via drmDMA\n",
current->pid, d.send_count); current->pid, d.send_count);
return -EINVAL; return -EINVAL;
} }
@ -1053,7 +1045,8 @@ int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
/* We'll send you buffers. /* We'll send you buffers.
*/ */
if (d.request_count < 0 || d.request_count > dma->buf_count) { if (d.request_count < 0 || d.request_count > dma->buf_count) {
DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_ERROR
("Process %d trying to get %d buffers (of %d max)\n",
current->pid, d.request_count, dma->buf_count); current->pid, d.request_count, dma->buf_count);
return -EINVAL; return -EINVAL;
} }