mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-04 20:08:29 +02:00
Stephane's port of Eric's race fix
This commit is contained in:
Keith Whitwell
parent
2cdfb2cc85
commit
08790293b1
2 changed files with 81 additions and 102 deletions
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@ -976,25 +976,26 @@ do { \
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} while (0)
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#define OUT_RING_USER_TABLE( tab, sz ) do { \
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#define OUT_RING_TABLE( tab, sz ) do { \
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int _size = (sz); \
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int __user *_tab = (tab); \
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int *_tab = (int *)(tab); \
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\
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if (write + _size > mask) { \
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int i = (mask+1) - write; \
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if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
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_tab, i*4 )) \
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return DRM_ERR(EFAULT); \
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int _i = (mask+1) - write; \
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_size -= _i; \
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while (_i > 0) { \
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*(int *)(ring + write) = *_tab++; \
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write++; \
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_i--; \
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} \
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write = 0; \
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_size -= i; \
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_tab += i; \
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_tab += _i; \
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} \
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while (_size > 0) { \
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*(ring + write) = *_tab++; \
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write++; \
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_size--; \
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} \
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\
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if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
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_tab, _size*4 )) \
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return DRM_ERR(EFAULT); \
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\
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write += _size; \
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write &= mask; \
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} while (0)
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@ -64,21 +64,6 @@ static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_p
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return 0;
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}
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static __inline__ int radeon_check_and_fixup_offset_user( drm_radeon_private_t *dev_priv,
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drm_file_t *filp_priv,
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u32 __user *offset ) {
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u32 off;
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DRM_GET_USER_UNCHECKED( off, offset );
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if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &off ) )
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return DRM_ERR( EINVAL );
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DRM_PUT_USER_UNCHECKED( offset, off );
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return 0;
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}
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static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv,
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drm_file_t *filp_priv,
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int id,
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@ -86,18 +71,16 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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switch ( id ) {
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case RADEON_EMIT_PP_MISC:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_DEPTHOFFSET
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- RADEON_PP_MISC ) / 4] ) ) {
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if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
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&data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
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DRM_ERROR( "Invalid depth buffer offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case RADEON_EMIT_PP_CNTL:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_COLOROFFSET
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- RADEON_PP_CNTL ) / 4] ) ) {
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if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
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&data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) {
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DRM_ERROR( "Invalid colour buffer offset\n" );
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return DRM_ERR( EINVAL );
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}
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@ -109,8 +92,8 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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case R200_EMIT_PP_TXOFFSET_3:
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case R200_EMIT_PP_TXOFFSET_4:
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case R200_EMIT_PP_TXOFFSET_5:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[0] ) ) {
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if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
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&data[0])) {
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DRM_ERROR( "Invalid R200 texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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@ -119,9 +102,8 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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case RADEON_EMIT_PP_TXFILTER_0:
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case RADEON_EMIT_PP_TXFILTER_1:
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case RADEON_EMIT_PP_TXFILTER_2:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_PP_TXOFFSET_0
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- RADEON_PP_TXFILTER_0 ) / 4] ) ) {
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if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
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&data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) {
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DRM_ERROR( "Invalid R100 texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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@ -135,9 +117,9 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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case R200_EMIT_PP_CUBIC_OFFSETS_5: {
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int i;
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for ( i = 0; i < 5; i++ ) {
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if ( radeon_check_and_fixup_offset_user( dev_priv,
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filp_priv,
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&data[i] ) ) {
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if (radeon_check_and_fixup_offset(dev_priv,
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filp_priv,
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&data[i])) {
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DRM_ERROR( "Invalid R200 cubic texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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@ -221,17 +203,11 @@ static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_
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drm_file_t *filp_priv,
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drm_radeon_cmd_buffer_t *cmdbuf,
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unsigned int *cmdsz ) {
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u32 tmp[4];
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u32 __user *cmd = (u32 __user *)cmdbuf->buf;
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u32 *cmd = (u32 *) cmdbuf->buf;
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if ( DRM_COPY_FROM_USER_UNCHECKED( tmp, cmd, sizeof( tmp ) ) ) {
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DRM_ERROR( "Failed to copy data from user space\n" );
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return DRM_ERR( EFAULT );
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}
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*cmdsz = 2 + ( ( tmp[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 );
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if ( ( tmp[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) {
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*cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
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if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
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DRM_ERROR( "Not a type 3 packet\n" );
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return DRM_ERR( EINVAL );
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}
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@ -242,32 +218,27 @@ static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_
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}
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/* Check client state and fix it up if necessary */
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if ( tmp[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */
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if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */
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u32 offset;
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if ( tmp[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
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if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
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| RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
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offset = tmp[2] << 10;
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offset = cmd[2] << 10;
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if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
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DRM_ERROR( "Invalid first packet offset\n" );
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return DRM_ERR( EINVAL );
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}
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tmp[2] = ( tmp[2] & 0xffc00000 ) | offset >> 10;
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cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
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}
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if ( ( tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) &&
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( tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
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offset = tmp[3] << 10;
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if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
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(cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
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offset = cmd[3] << 10;
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if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
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DRM_ERROR( "Invalid second packet offset\n" );
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return DRM_ERR( EINVAL );
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}
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tmp[3] = ( tmp[3] & 0xffc00000 ) | offset >> 10;
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}
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if ( DRM_COPY_TO_USER_UNCHECKED( cmd, tmp, sizeof( tmp ) ) ) {
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DRM_ERROR( "Failed to copy data to user space\n" );
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return DRM_ERR( EFAULT );
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cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
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}
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}
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@ -2451,7 +2422,7 @@ static int radeon_emit_packets(
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{
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int id = (int)header.packet.packet_id;
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int sz, reg;
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int __user *data = (int __user *)cmdbuf->buf;
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int *data = (int *)cmdbuf->buf;
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RING_LOCALS;
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if (id >= RADEON_MAX_STATE_PACKETS)
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@ -2472,7 +2443,7 @@ static int radeon_emit_packets(
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BEGIN_RING(sz+1);
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OUT_RING( CP_PACKET0( reg, (sz-1) ) );
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OUT_RING_USER_TABLE( data, sz );
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OUT_RING_TABLE(data, sz);
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ADVANCE_RING();
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cmdbuf->buf += sz * sizeof(int);
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@ -2486,7 +2457,6 @@ static __inline__ int radeon_emit_scalars(
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drm_radeon_cmd_buffer_t *cmdbuf )
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{
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int sz = header.scalars.count;
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int __user *data = (int __user *)cmdbuf->buf;
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int start = header.scalars.offset;
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int stride = header.scalars.stride;
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RING_LOCALS;
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@ -2495,7 +2465,7 @@ static __inline__ int radeon_emit_scalars(
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OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
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OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
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OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
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OUT_RING_USER_TABLE( data, sz );
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OUT_RING_TABLE(cmdbuf->buf, sz);
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ADVANCE_RING();
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cmdbuf->buf += sz * sizeof(int);
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cmdbuf->bufsz -= sz * sizeof(int);
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@ -2510,7 +2480,6 @@ static __inline__ int radeon_emit_scalars2(
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drm_radeon_cmd_buffer_t *cmdbuf )
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{
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int sz = header.scalars.count;
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int __user *data = (int __user *)cmdbuf->buf;
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int start = ((unsigned int)header.scalars.offset) + 0x100;
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int stride = header.scalars.stride;
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RING_LOCALS;
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@ -2519,7 +2488,7 @@ static __inline__ int radeon_emit_scalars2(
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OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
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OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
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OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
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OUT_RING_USER_TABLE( data, sz );
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OUT_RING_TABLE(cmdbuf->buf, sz);
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ADVANCE_RING();
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cmdbuf->buf += sz * sizeof(int);
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cmdbuf->bufsz -= sz * sizeof(int);
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@ -2532,7 +2501,6 @@ static __inline__ int radeon_emit_vectors(
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drm_radeon_cmd_buffer_t *cmdbuf )
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{
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int sz = header.vectors.count;
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int __user *data = (int __user *)cmdbuf->buf;
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int start = header.vectors.offset;
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int stride = header.vectors.stride;
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RING_LOCALS;
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@ -2541,7 +2509,7 @@ static __inline__ int radeon_emit_vectors(
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OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
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OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
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OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
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OUT_RING_USER_TABLE( data, sz );
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OUT_RING_TABLE(cmdbuf->buf, sz);
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ADVANCE_RING();
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cmdbuf->buf += sz * sizeof(int);
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@ -2556,7 +2524,6 @@ static int radeon_emit_packet3( drm_device_t *dev,
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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unsigned int cmdsz;
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int __user *cmd = (int __user *)cmdbuf->buf;
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int ret;
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RING_LOCALS;
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@ -2569,7 +2536,7 @@ static int radeon_emit_packet3( drm_device_t *dev,
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}
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BEGIN_RING( cmdsz );
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OUT_RING_USER_TABLE( cmd, cmdsz );
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OUT_RING_TABLE(cmdbuf->buf, cmdsz);
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ADVANCE_RING();
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cmdbuf->buf += cmdsz * 4;
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@ -2586,7 +2553,6 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t box;
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unsigned int cmdsz;
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int __user *cmd = (int __user *)cmdbuf->buf;
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int ret;
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drm_clip_rect_t __user *boxes = cmdbuf->boxes;
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int i = 0;
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@ -2628,7 +2594,7 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
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}
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BEGIN_RING( cmdsz );
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OUT_RING_USER_TABLE( cmd, cmdsz );
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OUT_RING_TABLE(cmdbuf->buf, cmdsz);
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ADVANCE_RING();
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} while ( ++i < cmdbuf->nbox );
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@ -2681,7 +2647,8 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
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int idx;
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drm_radeon_cmd_buffer_t cmdbuf;
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drm_radeon_cmd_header_t header;
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int orig_nbox;
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int orig_nbox, orig_bufsz;
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char *kbuf;
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LOCK_TEST_WITH_RETURN( dev, filp );
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@ -2699,23 +2666,28 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
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VB_AGE_TEST_WITH_RETURN( dev_priv );
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if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
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return DRM_ERR(EFAULT);
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if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
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return DRM_ERR(EINVAL);
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}
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if (cmdbuf.nbox &&
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DRM_VERIFYAREA_READ(cmdbuf.boxes,
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cmdbuf.nbox * sizeof(drm_clip_rect_t)))
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return DRM_ERR(EFAULT);
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/* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
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* races between checking values and using those values in other code,
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* and simply to avoid a lot of function calls to copy in data.
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*/
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orig_bufsz = cmdbuf.bufsz;
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if (orig_bufsz != 0) {
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kbuf = DRM(alloc)(cmdbuf.bufsz, DRM_MEM_DRIVER);
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if (kbuf == NULL)
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return DRM_ERR(ENOMEM);
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if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz))
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return DRM_ERR(EFAULT);
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cmdbuf.buf = kbuf;
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}
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orig_nbox = cmdbuf.nbox;
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while ( cmdbuf.bufsz >= sizeof(header) ) {
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if (DRM_GET_USER_UNCHECKED( header.i, (int __user *)cmdbuf.buf )) {
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DRM_ERROR("__get_user %p\n", cmdbuf.buf);
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return DRM_ERR(EFAULT);
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}
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header.i = *(int *)cmdbuf.buf;
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cmdbuf.buf += sizeof(header);
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cmdbuf.bufsz -= sizeof(header);
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@ -2724,7 +2696,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
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DRM_DEBUG("RADEON_CMD_PACKET\n");
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if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_packets failed\n");
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return DRM_ERR(EINVAL);
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goto err;
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}
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break;
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@ -2732,7 +2704,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
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DRM_DEBUG("RADEON_CMD_SCALARS\n");
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if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_scalars failed\n");
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return DRM_ERR(EINVAL);
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goto err;
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}
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break;
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@ -2740,7 +2712,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
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DRM_DEBUG("RADEON_CMD_VECTORS\n");
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if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_vectors failed\n");
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return DRM_ERR(EINVAL);
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goto err;
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}
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break;
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@ -2750,14 +2722,14 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
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if ( idx < 0 || idx >= dma->buf_count ) {
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DRM_ERROR( "buffer index %d (of %d max)\n",
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idx, dma->buf_count - 1 );
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return DRM_ERR(EINVAL);
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goto err;
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}
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buf = dma->buflist[idx];
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if ( buf->filp != filp || buf->pending ) {
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DRM_ERROR( "bad buffer %p %p %d\n",
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buf->filp, filp, buf->pending);
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return DRM_ERR(EINVAL);
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||||
goto err;
|
||||
}
|
||||
|
||||
radeon_cp_discard_buffer( dev, buf );
|
||||
|
|
@ -2767,7 +2739,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
|
|||
DRM_DEBUG("RADEON_CMD_PACKET3\n");
|
||||
if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) {
|
||||
DRM_ERROR("radeon_emit_packet3 failed\n");
|
||||
return DRM_ERR(EINVAL);
|
||||
goto err;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -2775,7 +2747,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
|
|||
DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
|
||||
if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) {
|
||||
DRM_ERROR("radeon_emit_packet3_clip failed\n");
|
||||
return DRM_ERR(EINVAL);
|
||||
goto err;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -2783,7 +2755,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
|
|||
DRM_DEBUG("RADEON_CMD_SCALARS2\n");
|
||||
if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
|
||||
DRM_ERROR("radeon_emit_scalars2 failed\n");
|
||||
return DRM_ERR(EINVAL);
|
||||
goto err;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -2791,21 +2763,27 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
|
|||
DRM_DEBUG("RADEON_CMD_WAIT\n");
|
||||
if (radeon_emit_wait( dev, header.wait.flags )) {
|
||||
DRM_ERROR("radeon_emit_wait failed\n");
|
||||
return DRM_ERR(EINVAL);
|
||||
goto err;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("bad cmd_type %d at %p\n",
|
||||
header.header.cmd_type,
|
||||
cmdbuf.buf - sizeof(header));
|
||||
return DRM_ERR(EINVAL);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (orig_bufsz != 0)
|
||||
DRM(free)(kbuf, orig_bufsz, DRM_MEM_DRIVER);
|
||||
DRM_DEBUG("DONE\n");
|
||||
COMMIT_RING();
|
||||
return 0;
|
||||
|
||||
err:
|
||||
if (orig_bufsz != 0)
|
||||
DRM(free)(kbuf, orig_bufsz, DRM_MEM_DRIVER);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue