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Cleaned up header file dependencies. Drivers still using old style DRM

Browse source 
extensions are now using the compatability module.
This commit is contained in:
Jens Owen 2002-04-03 02:40:31 +00:00
parent 36ee02682b
commit 07f9ee52e1
36 changed files with 834 additions and 358 deletions
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687
libdrm/xf86drmCompat.c
View file

@ -1,6 +1,5 @@
/* xf86drmCompat.c -- User-level interface to old DRM devices
/* xf86drmCompat.c -- User-level interface to old DRM device drivers
*
* Copyright 2000 VA Linx Systems, Inc., Fremont, California.
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
@ -23,10 +22,6 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Original Authors:
* Gareth Hughes <gareth@valinux.com>
* Kevin E. Martin <martin@valinux.com>
*
* Backwards compatability modules broken out by:
* Jens Owen <jens@tungstengraphics.com>
*
@ -78,6 +73,11 @@ extern int xf86RemoveSIGIOHandler(int fd);
#include "xf86drm.h"
#include "xf86drmCompat.h"
#include "drm.h"
#include "i810_drm.h"
#include "mga_drm.h"
#include "r128_drm.h"
#include "radeon_drm.h"
#include "sis_drm.h"
/* WARNING: Do not change, or add, anything to this file. It is only provided
@ -86,48 +86,633 @@ extern int xf86RemoveSIGIOHandler(int fd);
*/
/* I810 */
/*
drmI810CleanupDma
drmI810InitDma
*/
Bool drmI810CleanupDma(int driSubFD)
{
drm_i810_init_t init;
memset(&init, 0, sizeof(drm_i810_init_t));
init.func = I810_CLEANUP_DMA;
if(ioctl(driSubFD, DRM_IOCTL_I810_INIT, &init)) {
return 0; /* FALSE */
}
return 1; /* TRUE */
}
Bool drmI810InitDma(int driSubFD, drmCompatI810Init *info)
{
drm_i810_init_t init;
memset(&init, 0, sizeof(drm_i810_init_t));
init.func = I810_INIT_DMA;
init.mmio_offset = info->mmio_offset;
init.buffers_offset = info->buffers_offset;
init.ring_start = info->start;
init.ring_end = info->end;
init.ring_size = info->size;
init.sarea_priv_offset = info->sarea_off;
init.front_offset = info->front_offset;
init.back_offset = info->back_offset;
init.depth_offset = info->depth_offset;
init.overlay_offset = info->overlay_offset;
init.overlay_physical = info->overlay_physical;
init.w = info->w;
init.h = info->h;
init.pitch = info->pitch;
init.pitch_bits = info->pitch_bits;
if(ioctl(driSubFD, DRM_IOCTL_I810_INIT, &init)) {
return 0; /* FALSE */
}
return 1; /* TRUE */
}
/* Mga */
/*
drmMGAAgpBlit
drmMGACleanupDMA
drmMGAClear
drmMGAEngineReset
drmMGAFlushDMA
drmMGAFlushIndices
drmMGAFlushVertexBuffer
drmMGAFullScreen
drmMGAInitDMA
drmMGASwapBuffers
drmMGATextureLoad
*/
#define MGA_IDLE_RETRY 2048
int drmMGAInitDMA( int fd, drmCompatMGAInit *info )
{
drm_mga_init_t init;
memset( &init, 0, sizeof(drm_mga_init_t) );
init.func = MGA_INIT_DMA;
init.sarea_priv_offset = info->sarea_priv_offset;
init.sgram = info->sgram;
init.chipset = info->chipset;
init.maccess = info->maccess;
init.fb_cpp = info->fb_cpp;
init.front_offset = info->front_offset;
init.front_pitch = info->front_pitch;
init.back_offset = info->back_offset;
init.back_pitch = info->back_pitch;
init.depth_cpp = info->depth_cpp;
init.depth_offset = info->depth_offset;
init.depth_pitch = info->depth_pitch;
init.texture_offset[0] = info->texture_offset[0];
init.texture_size[0] = info->texture_size[0];
init.texture_offset[1] = info->texture_offset[1];
init.texture_size[1] = info->texture_size[1];
init.fb_offset = info->fb_offset;
init.mmio_offset = info->mmio_offset;
init.status_offset = info->status_offset;
init.warp_offset = info->warp_offset;
init.primary_offset = info->primary_offset;
init.buffers_offset = info->buffers_offset;
if ( ioctl( fd, DRM_IOCTL_MGA_INIT, &init ) ) {
return -errno;
} else {
return 0;
}
}
int drmMGACleanupDMA( int fd )
{
drm_mga_init_t init;
memset( &init, 0, sizeof(drm_mga_init_t) );
init.func = MGA_CLEANUP_DMA;
if ( ioctl( fd, DRM_IOCTL_MGA_INIT, &init ) ) {
return -errno;
} else {
return 0;
}
}
int drmMGAFlushDMA( int fd, drmLockFlags flags )
{
drm_lock_t lock;
int ret, i = 0;
memset( &lock, 0, sizeof(drm_lock_t) );
if ( flags & DRM_LOCK_QUIESCENT ) lock.flags |= _DRM_LOCK_QUIESCENT;
if ( flags & DRM_LOCK_FLUSH ) lock.flags |= _DRM_LOCK_FLUSH;
if ( flags & DRM_LOCK_FLUSH_ALL ) lock.flags |= _DRM_LOCK_FLUSH_ALL;
do {
ret = ioctl( fd, DRM_IOCTL_MGA_FLUSH, &lock );
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
if ( ret == 0 )
return 0;
if ( errno != EBUSY )
return -errno;
if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
/* Only keep trying if we need quiescence.
*/
lock.flags &= ~(_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL);
do {
ret = ioctl( fd, DRM_IOCTL_MGA_FLUSH, &lock );
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
}
if ( ret == 0 ) {
return 0;
} else {
return -errno;
}
}
int drmMGAEngineReset( int fd )
{
if ( ioctl( fd, DRM_IOCTL_MGA_RESET, NULL ) ) {
return -errno;
} else {
return 0;
}
}
int drmMGAFullScreen( int fd, int enable )
{
return -EINVAL;
}
int drmMGASwapBuffers( int fd )
{
int ret, i = 0;
do {
ret = ioctl( fd, DRM_IOCTL_MGA_SWAP, NULL );
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
if ( ret == 0 ) {
return 0;
} else {
return -errno;
}
}
int drmMGAClear( int fd, unsigned int flags,
unsigned int clear_color, unsigned int clear_depth,
unsigned int color_mask, unsigned int depth_mask )
{
drm_mga_clear_t clear;
int ret, i = 0;
clear.flags = flags;
clear.clear_color = clear_color;
clear.clear_depth = clear_depth;
clear.color_mask = color_mask;
clear.depth_mask = depth_mask;
do {
ret = ioctl( fd, DRM_IOCTL_MGA_CLEAR, &clear );
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
if ( ret == 0 ) {
return 0;
} else {
return -errno;
}
}
int drmMGAFlushVertexBuffer( int fd, int index, int used, int discard )
{
drm_mga_vertex_t vertex;
vertex.idx = index;
vertex.used = used;
vertex.discard = discard;
if ( ioctl( fd, DRM_IOCTL_MGA_VERTEX, &vertex ) ) {
return -errno;
} else {
return 0;
}
}
int drmMGAFlushIndices( int fd, int index, int start, int end, int discard )
{
drm_mga_indices_t indices;
indices.idx = index;
indices.start = start;
indices.end = end;
indices.discard = discard;
if ( ioctl( fd, DRM_IOCTL_MGA_INDICES, &indices ) ) {
return -errno;
} else {
return 0;
}
}
int drmMGATextureLoad( int fd, int index,
unsigned int dstorg, unsigned int length )
{
drm_mga_iload_t iload;
int ret, i = 0;
iload.idx = index;
iload.dstorg = dstorg;
iload.length = length;
do {
ret = ioctl( fd, DRM_IOCTL_MGA_ILOAD, &iload );
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
if ( ret == 0 ) {
return 0;
} else {
return -errno;
}
}
int drmMGAAgpBlit( int fd, unsigned int planemask,
unsigned int src_offset, int src_pitch,
unsigned int dst_offset, int dst_pitch,
int delta_sx, int delta_sy,
int delta_dx, int delta_dy,
int height, int ydir )
{
drm_mga_blit_t blit;
int ret, i = 0;
blit.planemask = planemask;
blit.srcorg = src_offset;
blit.dstorg = dst_offset;
blit.src_pitch = src_pitch;
blit.dst_pitch = dst_pitch;
blit.delta_sx = delta_sx;
blit.delta_sy = delta_sy;
blit.delta_dx = delta_dx;
blit.delta_dx = delta_dx;
blit.height = height;
blit.ydir = ydir;
do {
ret = ioctl( fd, DRM_IOCTL_MGA_BLIT, &blit );
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
if ( ret == 0 ) {
return 0;
} else {
return -errno;
}
}
/* R128 */
/*
drmR128CleanupCCE
drmR128Clear
drmR128EngineReset
drmR128FlushIndices
drmR128FlushIndirectBuffer
drmR128FlushVertexBuffer
drmR128FullScreen
drmR128InitCCE
drmR128PolygonStipple
drmR128ReadDepthPixels
drmR128ReadDepthSpan
drmR128ResetCCE
drmR128StartCCE
drmR128StopCCE
drmR128SwapBuffers
drmR128TextureBlit
drmR128WaitForIdleCCE
drmR128WriteDepthPixels
drmR128WriteDepthSpan
*/
#define R128_BUFFER_RETRY 32
#define R128_IDLE_RETRY 32
int drmR128InitCCE( int fd, drmCompatR128Init *info )
{
drm_r128_init_t init;
memset( &init, 0, sizeof(drm_r128_init_t) );
init.func = R128_INIT_CCE;
init.sarea_priv_offset = info->sarea_priv_offset;
init.is_pci = info->is_pci;
init.cce_mode = info->cce_mode;
init.cce_secure = info->cce_secure;
init.ring_size = info->ring_size;
init.usec_timeout = info->usec_timeout;
init.fb_bpp = info->fb_bpp;
init.front_offset = info->front_offset;
init.front_pitch = info->front_pitch;
init.back_offset = info->back_offset;
init.back_pitch = info->back_pitch;
init.depth_bpp = info->depth_bpp;
init.depth_offset = info->depth_offset;
init.depth_pitch = info->depth_pitch;
init.span_offset = info->span_offset;
init.fb_offset = info->fb_offset;
init.mmio_offset = info->mmio_offset;
init.ring_offset = info->ring_offset;
init.ring_rptr_offset = info->ring_rptr_offset;
init.buffers_offset = info->buffers_offset;
init.agp_textures_offset = info->agp_textures_offset;
if ( ioctl( fd, DRM_IOCTL_R128_INIT, &init ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128CleanupCCE( int fd )
{
drm_r128_init_t init;
memset( &init, 0, sizeof(drm_r128_init_t) );
init.func = R128_CLEANUP_CCE;
if ( ioctl( fd, DRM_IOCTL_R128_INIT, &init ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128StartCCE( int fd )
{
if ( ioctl( fd, DRM_IOCTL_R128_CCE_START, NULL ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128StopCCE( int fd )
{
drm_r128_cce_stop_t stop;
int ret, i = 0;
stop.flush = 1;
stop.idle = 1;
ret = ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop );
if ( ret == 0 ) {
return 0;
} else if ( errno != EBUSY ) {
return -errno;
}
stop.flush = 0;
do {
ret = ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop );
} while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
if ( ret == 0 ) {
return 0;
} else if ( errno != EBUSY ) {
return -errno;
}
stop.idle = 0;
if ( ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128ResetCCE( int fd )
{
if ( ioctl( fd, DRM_IOCTL_R128_CCE_RESET, NULL ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128WaitForIdleCCE( int fd )
{
int ret, i = 0;
do {
ret = ioctl( fd, DRM_IOCTL_R128_CCE_IDLE, NULL );
} while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
if ( ret == 0 ) {
return 0;
} else {
return -errno;
}
}
int drmR128EngineReset( int fd )
{
if ( ioctl( fd, DRM_IOCTL_R128_RESET, NULL ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128FullScreen( int fd, int enable )
{
drm_r128_fullscreen_t fs;
if ( enable ) {
fs.func = R128_INIT_FULLSCREEN;
} else {
fs.func = R128_CLEANUP_FULLSCREEN;
}
if ( ioctl( fd, DRM_IOCTL_R128_FULLSCREEN, &fs ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128SwapBuffers( int fd )
{
if ( ioctl( fd, DRM_IOCTL_R128_SWAP, NULL ) ) {
return -errno;
} else {
return 0;
}
}
int drmR128Clear( int fd, unsigned int flags,
unsigned int clear_color, unsigned int clear_depth,
unsigned int color_mask, unsigned int depth_mask )
{
drm_r128_clear_t clear;
clear.flags = flags;
clear.clear_color = clear_color;
clear.clear_depth = clear_depth;
clear.color_mask = color_mask;
clear.depth_mask = depth_mask;
if ( ioctl( fd, DRM_IOCTL_R128_CLEAR, &clear ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128FlushVertexBuffer( int fd, int prim, int index,
int count, int discard )
{
drm_r128_vertex_t v;
v.prim = prim;
v.idx = index;
v.count = count;
v.discard = discard;
if ( ioctl( fd, DRM_IOCTL_R128_VERTEX, &v ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128FlushIndices( int fd, int prim, int index,
int start, int end, int discard )
{
drm_r128_indices_t elts;
elts.prim = prim;
elts.idx = index;
elts.start = start;
elts.end = end;
elts.discard = discard;
if ( ioctl( fd, DRM_IOCTL_R128_INDICES, &elts ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128TextureBlit( int fd, int index,
int offset, int pitch, int format,
int x, int y, int width, int height )
{
drm_r128_blit_t blit;
blit.idx = index;
blit.offset = offset;
blit.pitch = pitch;
blit.format = format;
blit.x = x;
blit.y = y;
blit.width = width;
blit.height = height;
if ( ioctl( fd, DRM_IOCTL_R128_BLIT, &blit ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128WriteDepthSpan( int fd, int n, int x, int y,
const unsigned int depth[],
const unsigned char mask[] )
{
drm_r128_depth_t d;
d.func = R128_WRITE_SPAN;
d.n = n;
d.x = &x;
d.y = &y;
d.buffer = (unsigned int *)depth;
d.mask = (unsigned char *)mask;
if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128WriteDepthPixels( int fd, int n,
const int x[], const int y[],
const unsigned int depth[],
const unsigned char mask[] )
{
drm_r128_depth_t d;
d.func = R128_WRITE_PIXELS;
d.n = n;
d.x = (int *)x;
d.y = (int *)y;
d.buffer = (unsigned int *)depth;
d.mask = (unsigned char *)mask;
if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128ReadDepthSpan( int fd, int n, int x, int y )
{
drm_r128_depth_t d;
d.func = R128_READ_SPAN;
d.n = n;
d.x = &x;
d.y = &y;
d.buffer = NULL;
d.mask = NULL;
if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128ReadDepthPixels( int fd, int n,
const int x[], const int y[] )
{
drm_r128_depth_t d;
d.func = R128_READ_PIXELS;
d.n = n;
d.x = (int *)x;
d.y = (int *)y;
d.buffer = NULL;
d.mask = NULL;
if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128PolygonStipple( int fd, unsigned int *mask )
{
drm_r128_stipple_t stipple;
stipple.mask = mask;
if ( ioctl( fd, DRM_IOCTL_R128_STIPPLE, &stipple ) < 0 ) {
return -errno;
} else {
return 0;
}
}
int drmR128FlushIndirectBuffer( int fd, int index,
int start, int end, int discard )
{
drm_r128_indirect_t ind;
ind.idx = index;
ind.start = start;
ind.end = end;
ind.discard = discard;
if ( ioctl( fd, DRM_IOCTL_R128_INDIRECT, &ind ) < 0 ) {
return -errno;
} else {
return 0;
}
}
/* Radeon */
@ -423,9 +1008,17 @@ int drmRadeonFlushIndirectBuffer( int fd, int index,
}
/* SiS */
/*
drmSiSAgpInit
*/
Bool drmSiSAgpInit(int driSubFD, int offset, int size)
{
drm_sis_agp_t agp;
agp.offset = offset;
agp.size = size;
ioctl(driSubFD, SIS_IOCTL_AGP_INIT, &agp);
return 1; /* TRUE */
}
/* WARNING: Do not change, or add, anything to this file. It is only provided
* for binary backwards compatability with the old driver specific DRM

2
linux-core/i810_dma.c
View file

@ -33,6 +33,8 @@
#define __NO_VERSION__
#include "i810.h"
#include "drmP.h"
#include "drm.h"
#include "i810_drm.h"
#include "i810_drv.h"
#include <linux/interrupt.h> /* For task queue support */

24
linux-core/i810_drm.h
View file

@ -168,14 +168,34 @@ typedef struct _drm_i810_sarea {
} drm_i810_sarea_t;
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (xf86drmMga.h)
*/
/* i810 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t)
#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a)
#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b)
#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t)
#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d )
typedef struct _drm_i810_clear {
int clear_color;
int clear_depth;
int flags;
} drm_i810_clear_t;
/* These may be placeholders if we have more cliprects than
* I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
* false, indicating that the buffer will be dispatched again with a

2
linux-core/i810_drv.c
View file

@ -33,6 +33,8 @@
#include <linux/config.h>
#include "i810.h"
#include "drmP.h"
#include "drm.h"
#include "i810_drm.h"
#include "i810_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."

2
linux-core/i830_dma.c
View file

@ -34,6 +34,8 @@
#define __NO_VERSION__
#include "i830.h"
#include "drmP.h"
#include "drm.h"
#include "i830_drm.h"
#include "i830_drv.h"
#include <linux/interrupt.h> /* For task queue support */

13
linux-core/i830_drm.h
View file

@ -201,6 +201,19 @@ typedef struct _drm_i830_sarea {
int vertex_prim;
} drm_i830_sarea_t;
/* I830 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t)
#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t)
#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t)
#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43)
#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44)
#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t)
#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46)
#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t)
#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48)
typedef struct _drm_i830_clear {
int clear_color;
int clear_depth;

2
linux-core/i830_drv.c
View file

@ -34,6 +34,8 @@
#include <linux/config.h>
#include "i830.h"
#include "drmP.h"
#include "drm.h"
#include "i830_drm.h"
#include "i830_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."

2
linux-core/mga_drv.c
View file

@ -32,6 +32,8 @@
#include <linux/config.h>
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."

2
linux-core/r128_drv.c
View file

@ -32,6 +32,8 @@
#include <linux/config.h>
#include "r128.h"
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
#include "ati_pcigart.h"

2
linux-core/radeon_drv.c
View file

@ -30,6 +30,8 @@
#include <linux/config.h>
#include "radeon.h"
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include "ati_pcigart.h"

103
linux/drm.h
View file

@ -99,15 +99,6 @@ typedef struct drm_tex_region {
unsigned int age;
} drm_tex_region_t;
/* Seperate include files for the i810/mga/r128 specific structures */
#include "mga_drm.h"
#include "i810_drm.h"
#include "r128_drm.h"
#include "radeon_drm.h"
#include "sis_drm.h"
#include "i830_drm.h"
#include "gamma_drm.h"
typedef struct drm_version {
int version_major; /* Major version */
int version_minor; /* Minor version */
@ -428,100 +419,8 @@ typedef struct drm_scatter_gather {
#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
/* Device specfic ioctls should only be in their respective headers,
* however, a few device specific ioctls defined before XFree86 4.3
* are left here to preserve compatability. Do not add new device
* specific ioctls here.
*
/* Device specfic ioctls should only be in their respective headers
* The device specific ioctl range is 0x40 to 0x79. */
#define DRM_COMMAND_BASE 0x40
/* MGA specific ioctls */
#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
/* i810 specific ioctls */
#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t)
#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a)
#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b)
#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t)
#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d )
/* Rage 128 specific ioctls */
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t)
/* Radeon specific ioctls */
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t)
/* Gamma specific ioctls */
#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t)
#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t)
/* SiS specific ioctls */
#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
/* I830 specific ioctls */
#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t)
#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t)
#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t)
#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43)
#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44)
#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t)
#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46)
#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t)
#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48)
#endif

2
linux/gamma_dma.c
View file

@ -32,6 +32,8 @@
#define __NO_VERSION__
#include "gamma.h"
#include "drmP.h"
#include "drm.h"
#include "gamma_drm.h"
#include "gamma_drv.h"
#include <linux/interrupt.h> /* For task queue support */

10
linux/gamma_drm.h
View file

@ -48,6 +48,16 @@ typedef struct _drm_gamma_sarea {
int vertex_prim;
} drm_gamma_sarea_t;
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (xf86drmGamma.h)
*/
/* Gamma specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t)
#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t)
typedef struct drm_gamma_copy {
unsigned int DMAOutputAddress;
unsigned int DMAOutputCount;

2
linux/gamma_drv.c
View file

@ -32,6 +32,8 @@
#include <linux/config.h>
#include "gamma.h"
#include "drmP.h"
#include "drm.h"
#include "gamma_drm.h"
#include "gamma_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."

2
linux/i810_dma.c
View file

@ -33,6 +33,8 @@
#define __NO_VERSION__
#include "i810.h"
#include "drmP.h"
#include "drm.h"
#include "i810_drm.h"
#include "i810_drv.h"
#include <linux/interrupt.h> /* For task queue support */

24
linux/i810_drm.h
View file

@ -168,14 +168,34 @@ typedef struct _drm_i810_sarea {
} drm_i810_sarea_t;
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (xf86drmMga.h)
*/
/* i810 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t)
#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a)
#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b)
#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t)
#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d )
typedef struct _drm_i810_clear {
int clear_color;
int clear_depth;
int flags;
} drm_i810_clear_t;
/* These may be placeholders if we have more cliprects than
* I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
* false, indicating that the buffer will be dispatched again with a

2
linux/i810_drv.c
View file

@ -33,6 +33,8 @@
#include <linux/config.h>
#include "i810.h"
#include "drmP.h"
#include "drm.h"
#include "i810_drm.h"
#include "i810_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."

2
linux/i830_dma.c
View file

@ -34,6 +34,8 @@
#define __NO_VERSION__
#include "i830.h"
#include "drmP.h"
#include "drm.h"
#include "i830_drm.h"
#include "i830_drv.h"
#include <linux/interrupt.h> /* For task queue support */

13
linux/i830_drm.h
View file

@ -201,6 +201,19 @@ typedef struct _drm_i830_sarea {
int vertex_prim;
} drm_i830_sarea_t;
/* I830 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t)
#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t)
#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t)
#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43)
#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44)
#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t)
#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46)
#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t)
#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48)
typedef struct _drm_i830_clear {
int clear_color;
int clear_depth;

2
linux/i830_drv.c
View file

@ -34,6 +34,8 @@
#include <linux/config.h>
#include "i830.h"
#include "drmP.h"
#include "drm.h"
#include "i830_drm.h"
#include "i830_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."

2
linux/mga_dma.c
View file

@ -36,6 +36,8 @@
#define __NO_VERSION__
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#include <linux/interrupt.h> /* For task queue support */

15
linux/mga_drm.h
View file

@ -38,6 +38,7 @@
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (mga_sarea.h)
*/
#ifndef __MGA_SAREA_DEFINES__
#define __MGA_SAREA_DEFINES__
@ -225,6 +226,20 @@ typedef struct _drm_mga_sarea {
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (xf86drmMga.h)
*/
/* MGA specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
typedef struct _drm_mga_warp_index {
int installed;
unsigned long phys_addr;

2
linux/mga_drv.c
View file

@ -32,6 +32,8 @@
#include <linux/config.h>
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."

2
linux/mga_state.c
View file

@ -35,6 +35,8 @@
#define __NO_VERSION__
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#include "drm.h"

2
linux/mga_warp.c
View file

@ -30,6 +30,8 @@
#define __NO_VERSION__
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#include "mga_ucode.h"

2
linux/r128_cce.c
View file

@ -31,6 +31,8 @@
#define __NO_VERSION__
#include "r128.h"
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
#include <linux/interrupt.h> /* For task queue support */

21
linux/r128_drm.h
View file

@ -170,6 +170,27 @@ typedef struct drm_r128_sarea {
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (xf86drmR128.h)
*/
/* Rage 128 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t)
typedef struct drm_r128_init {
enum {
R128_INIT_CCE = 0x01,

2
linux/r128_drv.c
View file

@ -32,6 +32,8 @@
#include <linux/config.h>
#include "r128.h"
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
#include "ati_pcigart.h"

2
linux/r128_state.c
View file

@ -30,6 +30,8 @@
#define __NO_VERSION__
#include "r128.h"
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
#include "drm.h"
#include <linux/delay.h>

2
linux/radeon_cp.c
View file

@ -31,6 +31,8 @@
#define __NO_VERSION__
#include "radeon.h"
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include <linux/interrupt.h> /* For task queue support */

19
linux/radeon_drm.h
View file

@ -240,6 +240,25 @@ typedef struct {
* KW: actually it's illegal to change any of this (backwards compatibility).
*/
/* Radeon specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t)
typedef struct drm_radeon_init {
enum {
RADEON_INIT_CP = 0x01,

2
linux/radeon_drv.c
View file

@ -30,6 +30,8 @@
#include <linux/config.h>
#include "radeon.h"
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include "ati_pcigart.h"

3
linux/radeon_state.c
View file

@ -30,8 +30,9 @@
#define __NO_VERSION__
#include "radeon.h"
#include "drmP.h"
#include "radeon_drv.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include <linux/delay.h>

10
linux/sis_drm.h
View file

@ -2,6 +2,16 @@
#ifndef _sis_drm_public_h_
#define _sis_drm_public_h_
/* SiS specific ioctls */
#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
typedef struct {
int context;
unsigned int offset;

103
shared-core/drm.h
View file

@ -99,15 +99,6 @@ typedef struct drm_tex_region {
unsigned int age;
} drm_tex_region_t;
/* Seperate include files for the i810/mga/r128 specific structures */
#include "mga_drm.h"
#include "i810_drm.h"
#include "r128_drm.h"
#include "radeon_drm.h"
#include "sis_drm.h"
#include "i830_drm.h"
#include "gamma_drm.h"
typedef struct drm_version {
int version_major; /* Major version */
int version_minor; /* Minor version */
@ -428,100 +419,8 @@ typedef struct drm_scatter_gather {
#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
/* Device specfic ioctls should only be in their respective headers,
* however, a few device specific ioctls defined before XFree86 4.3
* are left here to preserve compatability. Do not add new device
* specific ioctls here.
*
/* Device specfic ioctls should only be in their respective headers
* The device specific ioctl range is 0x40 to 0x79. */
#define DRM_COMMAND_BASE 0x40
/* MGA specific ioctls */
#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
/* i810 specific ioctls */
#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t)
#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a)
#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b)
#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t)
#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d )
/* Rage 128 specific ioctls */
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t)
/* Radeon specific ioctls */
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t)
/* Gamma specific ioctls */
#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t)
#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t)
/* SiS specific ioctls */
#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
/* I830 specific ioctls */
#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t)
#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t)
#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t)
#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43)
#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44)
#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t)
#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46)
#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t)
#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48)
#endif

103
shared/drm.h
View file

@ -99,15 +99,6 @@ typedef struct drm_tex_region {
unsigned int age;
} drm_tex_region_t;
/* Seperate include files for the i810/mga/r128 specific structures */
#include "mga_drm.h"
#include "i810_drm.h"
#include "r128_drm.h"
#include "radeon_drm.h"
#include "sis_drm.h"
#include "i830_drm.h"
#include "gamma_drm.h"
typedef struct drm_version {
int version_major; /* Major version */
int version_minor; /* Minor version */
@ -428,100 +419,8 @@ typedef struct drm_scatter_gather {
#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
/* Device specfic ioctls should only be in their respective headers,
* however, a few device specific ioctls defined before XFree86 4.3
* are left here to preserve compatability. Do not add new device
* specific ioctls here.
*
/* Device specfic ioctls should only be in their respective headers
* The device specific ioctl range is 0x40 to 0x79. */
#define DRM_COMMAND_BASE 0x40
/* MGA specific ioctls */
#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
/* i810 specific ioctls */
#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t)
#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a)
#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b)
#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t)
#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d )
/* Rage 128 specific ioctls */
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t)
/* Radeon specific ioctls */
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t)
/* Gamma specific ioctls */
#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t)
#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t)
/* SiS specific ioctls */
#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
/* I830 specific ioctls */
#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t)
#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t)
#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t)
#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43)
#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44)
#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t)
#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46)
#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t)
#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48)
#endif