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fix PCI and AGP posting problems (based on testing by Chris Ison and

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suggestions by Benjamin Herrenschmidt and Arjan van de Ven)
remove radeon_flush_write_combine() which has been unused for a while
This commit is contained in:
Michel Daenzer 2003-02-04 19:25:13 +00:00
parent 164485d34a
commit 0618c131c5
2 changed files with 14 additions and 18 deletions
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16
shared-core/radeon_drv.h
View file

@ -823,13 +823,6 @@ do { \
* Ring control
*/
#if defined(__powerpc__)
#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
#else
#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER()
#endif
#define RADEON_VERBOSE 0
#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
@ -863,8 +856,13 @@ do { \
dev_priv->ring.tail = write; \
} while (0)
#define COMMIT_RING() do { \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
#define COMMIT_RING() do { \
/* Flush writes to ring */ \
DRM_READMEMORYBARRIER(); \
GET_RING_HEAD( &dev_priv->ring ); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
/* read from PCI bus to ensure correct posting */ \
RADEON_READ( RADEON_CP_RB_RPTR ); \
} while (0)
#define OUT_RING( x ) do { \

16
shared/radeon_drv.h
View file

@ -823,13 +823,6 @@ do { \
* Ring control
*/
#if defined(__powerpc__)
#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
#else
#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER()
#endif
#define RADEON_VERBOSE 0
#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
@ -863,8 +856,13 @@ do { \
dev_priv->ring.tail = write; \
} while (0)
#define COMMIT_RING() do { \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
#define COMMIT_RING() do { \
/* Flush writes to ring */ \
DRM_READMEMORYBARRIER(); \
GET_RING_HEAD( &dev_priv->ring ); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
/* read from PCI bus to ensure correct posting */ \
RADEON_READ( RADEON_CP_RB_RPTR ); \
} while (0)
#define OUT_RING( x ) do { \