diff --git a/src/drm/cairo-drm-i915-shader.c b/src/drm/cairo-drm-i915-shader.c
index 7c1291ade..d22c1c5db 100644
--- a/src/drm/cairo-drm-i915-shader.c
+++ b/src/drm/cairo-drm-i915-shader.c
@@ -1362,6 +1362,7 @@ i915_shader_acquire_surface (i915_shader_t *shader,
     cairo_filter_t filter;
     cairo_matrix_t m;
     int src_x = 0, src_y = 0;
+    cairo_status_t status;
 
     assert (src->type.fragment == (i915_fragment_shader_t) -1);
     drm = surface = pattern->surface;
@@ -1403,6 +1404,12 @@ i915_shader_acquire_surface (i915_shader_t *shader,
 		cairo_surface_subsurface_t *sub = (cairo_surface_subsurface_t *) surface;
 		int x;
 
+		if (s->intel.drm.fallback != NULL) {
+		    status = intel_surface_flush (s);
+		    if (unlikely (status))
+			return status;
+		}
+
 		if (to_intel_bo (s->intel.drm.bo)->batch_write_domain) {
 		    /* XXX pipelined flush of RENDER/TEXTURE cache */
 		}
@@ -1433,6 +1440,13 @@ i915_shader_acquire_surface (i915_shader_t *shader,
 	    if (s->intel.drm.base.device == shader->target->intel.drm.base.device &&
 		s != shader->target)
 	    {
+		if (s->intel.drm.fallback != NULL) {
+		    status = intel_surface_flush (s);
+		    if (unlikely (status))
+			return status;
+		}
+
+
 		src->type.fragment = FS_TEXTURE;
 		src->surface.pixel = NONE;
 		surface_width  = s->intel.drm.width;
diff --git a/src/drm/cairo-drm-i965-shader.c b/src/drm/cairo-drm-i965-shader.c
index fc9ae5708..c448d8886 100644
--- a/src/drm/cairo-drm-i965-shader.c
+++ b/src/drm/cairo-drm-i965-shader.c
@@ -442,6 +442,12 @@ i965_shader_acquire_surface (i965_shader_t *shader,
 		if (s != shader->target) {
 		    int x;
 
+		    if (s->intel.drm.fallback != NULL) {
+			status = intel_surface_flush (s);
+			if (unlikely (status))
+			    return status;
+		    }
+
 		    if (to_intel_bo (s->intel.drm.bo)->batch_write_domain)
 			i965_pipelined_flush (i965_device (s));
 
@@ -510,6 +516,12 @@ i965_shader_acquire_surface (i965_shader_t *shader,
 	} else {
 	    if (s->intel.drm.base.device == shader->target->intel.drm.base.device) {
 		if (s != shader->target) {
+		    if (s->intel.drm.fallback != NULL) {
+			status = intel_surface_flush (s);
+			if (unlikely (status))
+			    return status;
+		    }
+
 		    if (to_intel_bo (s->intel.drm.bo)->batch_write_domain)
 			i965_pipelined_flush (i965_device (s));